RM57L843: EMIF Synchronous Interface doesn't support Burst Length 8?

Background Brief:

• A custom board that RM57 connects a 16bit SDRAM (Let me call it BOARD1 for short).
• Another custom board that RM57 connects a FPGA via EMIF Synchronous Interface. (Let me call it BOARD2 for short).

Environment:

• HALCOGEN 4.7.0
• TI ARM Compiler 16.9.4
• CCS 7.3

EMIF Configuration:

Testing Codes:

• CODE_R32 - read 32 bytes from EMIF address.

  • void test_ldm32(uint32_t addr) {
        asm("\tSTMFD sp!, {r3-r10}");
        asm("\tLDMIA r0!, {r3-r10}");
        asm("\tLDMFD sp!, {r3-r10}");
    }

• CODE_R16 - read 16 bytes from EMIF address.

  • void test_ldm16(uint32_t addr) {
        asm("\tSTMFD sp!, {r3-r6}");
        asm("\tLDMIA r0!, {r3-r6}");
        asm("\tLDMFD sp!, {r3-r6}");
    }

• CODE_R8 - read 8 bytes from EMIF address.

  • void test_ldm8(uint32_t addr) {
        asm("\tSTMFD sp!, {r3-r4}");
        asm("\tLDMIA r0!, {r3-r4}");
        asm("\tLDMFD sp!, {r3-r4}");
    }

• CODE_R4 - read 4 bytes from EMIF address.

  • void test_ldm4(uint32_t addr) {
        asm("\tSTMFD sp!, {r3}");
        asm("\tLDMIA r0!, {r3}");
        asm("\tLDMFD sp!, {r3}");
    }

• CODE_W32 - write 32 bytes to EMIF address.

  • void test_stm32(uint32_t addr) {
        asm("\tSTMFD sp!, {r3-r10}");
        asm("\tSTMIA r0!, {r3-r10}");
        asm("\tLDMFD sp!, {r3-r10}");
    }

• All the testing codes above use 0x80000000 as input parameter. So the address must be aligned to 16 bytes.

Problem Details:

• BOARD1: use oscilloscope to detect signals only on EMIF_CLK and EMIF_nDQM[0] for simplicity.
  • CODE_R32:
    • As we know the nDQM signal is used to select the valid bytes in the BURST READ transaction. And we can see there are 4 groups of valid nDQM signals. Each group lasts 4 CLK periods, which means the BURST LENGTH is 4, not 8. Then the total transaction count is 4x4=16, thus 32 bytes, which is just the expected.
  • CODE_R16:
    • As we can see the BURST LENGTH is 4 and total transaction count is 4x2=8, thus 16 bytes. 
  • CODE_R8: No screenshot unfortunately. The BURST LENGTH is 4 and total transaction count is 4, thus 8 bytes.
  • CODE_R4: No screenshot unfortunately. The BURST LENGTH is 2 and total transaction count is 2, thus 4 bytes.
  • CODE_W32:
    • 
    • This is similar to the situation of CODE_R32.
• BOARD2; use FPGA automatically graph the signals.
  • CODE_R32:
    
    • 
    • As we can see, there are 2 BURST READ group. In each BURST group, the nDQM lasts 4 CLK periods, and nWE is pulled low at some point, which means a BURST TERMINATE is signalled. Then I can be sure that the BURST READ is terminated early.

Question:

• This problem significantly affects the RAM r/w performance. Does this problem has an workaround?
• We have another custom board using RM48L952 connecting FPGA via EMIF synchronous interface. But RM48 works fine that BURST LENGTH is able to be the expected 8, without nWE is pulled low early. The EMIF controllers in RM48 and RM57 seem very similar to each other. Why do they have such different behavior?