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TM4C123GH6PM: I2C Communication with a 5V Slave

Joshua Moskowitz
Prodigy 140 points
Part Number: TM4C123GH6PM


This is probably a pretty basic question, but I couldn't find an answer.  I'm using a TM4C123GH6PM microcontroller to talk to a slave device that requires 5V logic.  I'm currently using a level shifter IC to handle the difference between the MCU's 3.3V and the slave's 5V, but I'd like to eliminate this part for reasons of cost and simplifying the design.

My question is: can I pull the I2C pins of the MCU up to 5V and directly connect them to the slave's pins?  In the datasheet on page 1358 table 24-1 states that the maximum voltage that can be applied to a GPIO is 5.5V, but then note "e" send me to page 1385 which says that the GPIO pins are only 5V tolerant when configured as inputs.

So, when pins are configured to the I2C peripheral, are they technically inputs, outputs, something in between?  I know I2C by design is bidirectional, so I don't know. Digging into the I2C sections of the datasheet didn't help clarify anything for me. 

Thanks in advance for your help.

  • 0
    TI__Guru**** 191906 points

    Hi Joshua,
    The 5.5V is the absolute maximum beyond which the pin may be damaged. Even if the pin is 5V tolerant I will not suggest you do away with the level shifter. There is some tolerance on regulator supplying the 5V. Let's say 5% tolerance will give a 5.25V on the input to the pin. Other spikes/noise on the supply can act the same way. I can image reliability issue down the row for prolonged operation.

  • 0 in reply to Charles Tsai
    Prodigy 140 points
    Charles, thanks for your reply and advice. I understand and agree with your recommendation. However, it doesn't directly answer my question. That question is, are the GPIO pins actually 5V tolerant when configured to use the I2C peripheral?
  • 0 in reply to Charles Tsai
    Guru 117855 points

    Greetings Charles,

    Very well advised - I'd say.     We've had clients "attempt" such (use of a 5V Slave, I2C device) - and just as you hint - headroom is slight - risk thus high - what "savings" (then) can be claimed?

    Poster may ask, "Just why do so many semi-vendors produce such "level shifters" - if their use is "optional?"     Clearly - they provide value - prevent difficulty. 

    Poster speaks to, "cost down & simplification" - are not BOTH ACHIEVED via use of a (more proper) 3V3 I2C Slave?       Many are available - more arrive each week - a proper investigation is likely to find a, "3V3" thus "level-shift-FREE" suitable I2C device...

  • 0 in reply to Charles Tsai
    Mastermind 8695 points
    I2C pins act like open collectors (or open drain for FETs) instead of a GPIO output.

    I2C pins don't drive the line high; The pins only sink current which is why you need 10K pull ups on the bus.
  • 0 in reply to Peter Borenstein
    Guru 117855 points

    Peter Borenstein said:
    which is why you need 10K pull ups

    10K is one value which usually succeeds.    However "bus-load", capacitance and pcb trace distance - may all conspire to demand "other" values.
    Each situation is unique - there is not universal "need" for any particular value...     (to include - 10K)

  • 0 in reply to Joshua Moskowitz
    TI__Guru**** 191906 points
    Joshua,
    Yes, all GPIO signals are 5-V tolerant when configured as inputs except for a few pins which are limited to 3.6V. With that said, I will still suggest level shifters to alleviate any risks associated with reliability on the field.
  • 0 in reply to cb1_mobile
    Prodigy 140 points

    "Poster speaks to, "cost down & simplification" - are not BOTH ACHIEVED via use of a (more proper) 3V3 I2C Slave?       Many are available - more arrive each week - a proper investigation is likely to find a, "3V3" thus "level-shift-FREE" suitable I2C device..."

    I'm sorry, but this is not the case.  Without getting too deep into the proprietary nature of my application, there is no alternative slave device that operates at the 3.3V logic level.

  • 0 in reply to Joshua Moskowitz
    Prodigy 140 points

    I also understand the open drain concept and the need for pull up resistors.  But on page 999 of the datasheet it specifically states not to configure the SCL pin as an open drain "Due to the internal circuitry that supports high-speed operation".  To me what that translates to is I have no idea what's going on inside and whether or not that pin is configured as an input.

    It sounds like everyone thinks it's a terrible idea and I likely won't do away with the level shifter as a result,  but the underlying question remains.

    Are GPIO pins configured to I2C considered "inputs" for the purpose of determining the allowable absolute maximum voltage? 

  • 0 in reply to Peter Borenstein
    Mastermind 8695 points

    To answer half of Josh's question, no, I2C pins are not GPIO. Figure 10-1 shows how different circuitry can be connected to the pad depending on your register settings.

    The data sheet gives you table 24-33 showing a different set of limits based on the pad being configured as an ADC. I expected to find a separate table for every peripheral option.

    I also expect an open drain output to have a much higher voltage tolerance than GPIO, which is a hopeful thought for your application.

  • 0 in reply to Peter Borenstein
    Prodigy 140 points
    Thanks Peter. If I understand what you're saying, once I configure a specific pad/pin to be I2C it is by definition no longer a GPIO and therefore the GPIO specific limits would not apply. Correct?

    I see what you mean in Table 24-33. A cursory skim through the datasheet didn't turn up a similar table for the I2C peripheral, but all that probably means is I just need to spend a little more time digging through the 1409 pages.
  • 0 in reply to Joshua Moskowitz
    Mastermind 8695 points

    Correct, you understand what I mean. Though I may be wrong...

    The I2C table would be under the "Electrical Characteristics" chapter if it exists. I think you are entitled to an explanation! (biased opinion)

    Table 24-30 has a note g that reads "If the I/O pad is not voltage limited, it should be current limited (to IINJ+ and IINJ-)". More hope! I hope someone at TI gives us the I2C pad information, or explains our misunderstanding.

  • 0 in reply to Peter Borenstein
    Prodigy 140 points

    Hmmm, that's interesting.  If I'm interpreting the information in table 24-30 correctly, that would mean current must be limited to 100 uA.  At 5V that would equate to a pull up resistor value of 50k which I don't think the I2C bus would be too happy about.

    I do hope we get an official answer on this.

  • 0 in reply to Joshua Moskowitz
    TI__Guru**** 191906 points

    The 100uA in table 24-30 is the input "leakage" current under the specified voltage range which normally/mainly are contributed by the input protection circuitry. This is not to say it limits the input current to 100uA.

    I will get more info on the pad when used as an I2C. For the moment, I think the GPIO spec limits still apply when used as a I2C. ADC pads have different spec because they are of different design for analog function rather than digital.

  • 0 in reply to Peter Borenstein
    Guru 27665 points

    Peter Borenstein said:
    I also expect an open drain output to have a much higher voltage tolerance than GPIO, which is a hopeful thought for your application.

    I think that expectation comes from assuming the limit is due to the top half of the totem pole and that being disconnected in an open drain configuration?

    I would not share that expectation. Although the upper half of the totem must surely be turned off it may (seems likely) still be connected so its limits may still apply and I don't think there is any reason to think that other sensitive circuitry has been disconnected either. I can even envision cases where the 'high  voltage' protection that enables 5V tolerance for GPIO is effectively disabled in an open drain configuration (not convinced that's likely though) and all of that assumes that the limitation isn't coming from the voltage limitations of the lower half of the totem pole.

    Certainly that voltage tolerance should be in the data sheet though (or worst case in the user manual).

    Robert

  • 0 in reply to Robert Adsett
    Mastermind 8695 points
    I was thinking of open drain outputs using discrete FETs. It's rare to see an N-channel FET with a Vdss of less than 8V.

    In addition to the ADC pins, the USB pins also have a different voltage limit, but that limit is called out in the text "All GPIO signals are 5-V tolerant when configured as inputs except for PD4, PD5, PB0 and PB1, which are limited to 3.6 V"
  • 0 in reply to Peter Borenstein
    TI__Guru**** 191906 points
    Hi Peter,
    Sorry, I forgot to follow up the thread. I did talk to our expert the other day but I just forgot to relate his answer here. As far as if the GPIO limits will apply when used as as I2C signal, the answer is yes.