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TMS570LC4357: CPU Interconnect Arbitration Policy

Franck WARTEL
Intellectual 450 points
Part Number: TMS570LC4357

Hello,


I would need some detailed information regarding the arbitration policy applied at CPU Interconnect level so that to finely compute the penalties to be taken into account when multiple requests from multiple masters are pending.

I cannot find such pieces of information in the TMS570LC43xx TRM, in the TLS570LC4357 datasheet or in this forum.

Can you please guide me to a document where the CPU and Peripheral Interconnects arbitration policies and potential configurability are described or provide me with those elements ?

Thanks for your support,

Best Regards,

Franck.

  • 0
    TI__Guru 59540 points
    Hello Frank,

    I will need to check with my colleagues to see if this level of detail exists and, if so, where it would be documented.
  • 0
    TI__Guru 59540 points

    Hello Frank,

    I apologize for the delay in getting back to you on this. We do not have any specific documents regarding the arbitration scheme other than what is included in the TRM and datasheets. In general the arbitration scheme in the interconnect is round-robin.  The interconnect is a multi-bus such that multiple masters to different slaves can be carried out in parallel. Arbitration at each slave instance is needed when multiple masters are access the same slave at the same time. 

    The attached slides below also demonstrate several examples of parallel access by bus masters to different L2 and L3 components.

    8863.TMS570LC43xx_System_Architecture_parallel_accesses.pdf

  • 0 in reply to Chuck Davenport
    Intellectual 450 points

    Hi Chuck,

    Thanks for the answer  and the clarification regarding the fact that transfers from different sources to different masters can be executed in parallel.

    Focusing on EMIF slave, do you confirm that the chapter 21.2.2 of TMS570LC43x_TRM is describing the priorization performed at CPU interconnect level  (i.e crossbar = CPU interconnect)

    Thanks,

    Franck.

  • 0 in reply to Franck WARTEL
    TI__Guru 59540 points

    Focusing on EMIF slave, do you confirm that the chapter 21.2.2 of TMS570LC43x_TRM is describing the priorization performed at CPU interconnect level  (i.e crossbar = CPU interconnect)

    This is a correct statement. The referenced interconnect is the CPU interconnect/crossbar