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TM4C123GH6PM: SSI Free scale SPI frame format receive buffer timeout

Ravi Ranjan Kishor
Prodigy 20 points
Part Number: TM4C123GH6PM

Hello Team,

I am writing SSI driver for the Freescale frame format and I could not understand the reference manual description about the receive buffer time out.

My understanding : The timeout count is started when receive buffer goes from empty to non empty state. And if the receive buffer is emptied before the timeout then ISR shall clear the timeout interrrupt.

Question : 1. Which ISR here the reference manual is talking about(Is this the receive buffer empty ISR ?)

                 2. If the receive buffer is not empty and timeout happens then is it possible to read the buffer in the timeout ISR?(Scenario if there are only two entries in receive buffer then the only interrupt which can be triggered is the receive buffer time out and in the corresponding ISR the data register can be read.Do I need to clear the timeout interrupt here? )

regards,

Ravi Ranjan Kishor

  • 0
    TI__Guru**** 191076 points

    Hi Ranjan,

      This is talking about the timeout interrupt. When the receive FIFO changes from empty to non-empty, the timeout counter starts counting until the FIFO becomes empty. If the FIFO is not empty before the counter times out the timeout interrupt is generated. In the timeout ISR you want to read the remaining FIFO and then clear the timeout interrupt flag. Yes, you must clear the timeout interrupt flag in the ISR.

  • 0 in reply to Charles Tsai
    Prodigy 20 points

    Hello Charles,

    Understood. Thank you for the reply and good explanation.

    regards,

    Ravi Ranjan Kishor