Hello,
I have some questions regarding input overshoot on the TMS570LS3137.
Using your TMS570LS3137 IBIS model, our Hyperlynx signal integrity fast-strong simulations show we are violating the datasheet spec VI < VSSIO - 0.3V or VI > VCCIO + 0.3V, and input clamp current spec +/-3.5mA. We are simulating with a standard 3.3V CMOS driver model that is properly series terminated with 33ohms into a 50ohm trace impedance. For example, the simulation shows the overshoot below ground to be -368mV peak for about 300ps below -0.3V, and the input current to peak at -24mA and is greater than the -3.5mA spec for about 570ps. But when I edit your IBIS model to change the pin inductance and capacitance values to 0nH and 0pF for Lpin and Cpin and re-simulate, the input current spike is now reduced to about -13mA. And then when I change your IBIS model's die capacitance value to 0pF for C_comp and re-simulate, the input current now is only about -20uA peak, with the duration of the current spike to be about 945ps, which is about the same time the input voltage is now below -0.3V, and now peaks at about -331mV.
So does this mean that the higher current spikes of -24mA is mainly due to the package and die parasitics and are not from the input diode clamp current and the input clamp current we are seeing is really only about -20uA peak?
Does this mean that we really are not seeing an overshoot problem if the clamp current is really only -20uA even though the voltage is going below -0.3V?
If the -24mA is really input diode clamp current, would this still be an overshoot problem since it is only happening for about 0.5ns per transition as described above? The -3.5mA and -0.3V specs are really DC specs and are not dynamic overshoot specs right?
Please advise if we are really seeing an overshoot problem in our simulations or not and what we should do about them if they are. We are already properly terminating them in our sims so I'm not sure what else we can do.
Thanks,
Scott
