RM57L843: rm57l843

Raheel,

Raheel Bari said:

1)- The datasheet of RM57L843 says the number of eight-bit GIO Ports are only two with 16 interrupts and having 161 GPIO in total. While the doc spnu562 considers the possibility of 08 ports of eight bit with 32 interrupts possible. It means that all the 145 pins are only available on the pin basis when not used in their original functionality or they can be used on the port basis.

Hercules has dedicated GPIO as you have noted. In the RM57 device there is a GIOA and GIOB port with 8 pins each. Also each of the dedicated GIO pins have interrupt capability to allow some form of external interrupt capability.

In addition, many of our peripheral modules have the capability of being used in a GPIO or non-functional mode. This means in the case of the RM57 there are up to a total of 145 GPIO capable pins (including the 16 dedicated GPIO pins). The key phrase here is "up to" which means there will have to be decisions made regarding functional vs. non-functional use of the pins as well as mux options that may mean to choose a certain pin function over another via the pinmux controller.

In reference to your comment regarding the 8 GPIO ports, there are provisions in the IP of the GPIO module to support up to 8 dedicated ports but this is a device level consideration at design time and not a user configuration option. Often, our IP chapters are written to the spec of the module IP as a superset capability and not narrowed to the device level capability. For certain, these incidences where we do this can be confusing and we try to clean these up as we find them. Please feel free to submit a document feedback using the link at the bottom of each page for cases where we need to add clarity or clean up a superset feature such as this to narrow the scope to the device implementation.

Raheel Bari said:

2)- The datasheet says that it provides three CS of Async interface providing 16MB on each of the three CS on EMIF, while the document spnu562 does specify the provision of external memory with GPIO without mentioning any size. When I asked for the support, I have been told that 64MB is possible (as the address range also confirm this). I'm confused with the page 90 of datasheet where it claims to have 64MB frame size and 16MB of actual size. What is the difference between the frame and actual size? and is it possible to use the 64MB 16-bit device?

The frame size associated with each of the CS is the architectural consideration or capability of the IP where the actual size is the physically implemented size for the CS. So, if we consider the table content, you could have three separate memories with 16MB each (CS[4:2]) or one with 128MB for CS0. given CS1 is not implemented, I don't see a way to get to 64MB by itself unless you tie off some of the address lines to create a wrap around scenario for the 128MB option.

Chuck


Thanks for the detailed response.

About Question 01, on the page 08 of datasheet it has been mentioned total GPIO are 168 with 16 pins available as interrupt available. Could you please explain me why it has been mentioned as 168 instead of 145 ? Can i have the details of those peripherals whose pins can be used as GPIO along with their normal functionality and those which can't be used as an GPIO. I try to extract the information from page 15 to page 39 but i could not final total of 145 or 168.

About Question 02, I agree to your point that unless i create a wrap around using GPIO or by someother means it isn't possible to connect 64MB with the current address lines.

Please update me more on Question 01, Question 02 is clear.

REgards;

I seek more explaination on Question 01