RTOS/TM4C123GH6PM: Trouble configuring ADC and uDMA for continuous transfer; ADC int won't trigger

I'm trying to configure the uDMA to transfer 1024 values (16 bits each). I'm having some trouble as the code won't get the ADC INT to trigger. I have a breakpoint in the interrupt and it never reaches it.

The ADC is being triggered by a Timer and I would like the uDMA to capture a value everytime it gets triggered. Is there something wrong in the initialization code? Thank you

Also, I'm trying to use ADC0 and Sequencer 3. So it will be capture 1 value. In addition, my sampling rate is approx 50 kHz.

Thank you, I really appreciate it

Tool/software: TI-RTOS

void ConfigureADCandDMA(void) {
    // Enable uDMA and ADC peripheral
    SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
    SysCtlPeripheralReset(SYSCTL_PERIPH_ADC0);
    ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, 30);

    // uDMA initialize
    ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_TIMER, 0);
    ADCSequenceStepConfigure(ADC0_BASE, 3, 0, ADC_CTL_CH8 | ADC_CTL_IE | ADC_CTL_END);

    ADCSequenceDMAEnable(ADC0_BASE, 3);


    // #####################################################


    SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
    SysCtlPeripheralReset(SYSCTL_PERIPH_UDMA);

    uDMAEnable();
    uDMAControlBaseSet(sControlTable);

    uDMAChannelAttributeDisable(UDMA_CHANNEL_ADC0, UDMA_ATTR_ALL);

    uDMAChannelAttributeEnable(UDMA_CHANNEL_ADC0, UDMA_ATTR_USEBURST /*only allow burst transfers*/);

    uDMAChannelControlSet(UDMA_CHANNEL_ADC0 | UDMA_PRI_SELECT,
                          UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_1024);

    uDMAChannelTransferSet(UDMA_CHANNEL_ADC0 | UDMA_PRI_SELECT,
                           UDMA_MODE_BASIC,
                           (void *)(ADC0_BASE + ADC_O_SSFIFO3),
                           g_ulADCValues, 1023);

    uDMAChannelEnable(UDMA_CHANNEL_ADC0);
    IntEnable(INT_UDMAERR);
    IntEnable(INT_UDMA);

    IntEnable(INT_ADC0SS3);

    ADCIntEnableEx(ADC0_BASE, ADC_INT_DMA_SS3);

    ADCSequenceEnable(ADC0_BASE, 3);
//  ADCIntEnable(ADC0_BASE, 3);
    ADCIntClear(ADC0_BASE, 3);

}