TM4C123GH6PM: Newbie needs help setting up ADC with uDMA

Savo, please see the following for some snippets of my ADC DMA implementation. Please note I use a TM4C1294NCPDT, so be aware. Also, I don't want to hold your hand in a total-sense by providing copy-paste cookie-cutter code. You'll have to declare the missing variables in appropriate areas. I've tried to comment the code to assist the best I can. I'm not the best programmer, but hopefully this may help you.

Couple of vars to get you going:

#define DMA_SAMPLING_FREQ           256000 // Use this for VIRTUAL 16-bit sampling at 1000Hz

// Sampling Rate, determines what frequency to make Timer0A trigger an ADC sample
uint32_t g_uiSamplingFreq = DMA_SAMPLING_FREQ;

Main loop:

// Somewhere in setup/config...
// Initialize everything needed for sampling ADC with DMA, triggered by a timer
init_ADC_DMA_SampleTimer();

// Somewhere in main()...
// DMA Sampling
DMA_Sample_Start(NUM_DMA_SAMPLES);

// Wait until DMA Data is ready
while (g_ucDataReady == 0)
{
};

// If we have new DMA data, handle it
if (g_ucDataReady)
{
    Process_Your_Data();
}

Here's the detailed functions...

bool init_ADC_DMA_SampleTimer(void){
    ////////////// Peripheral Init //////////////////
    // This is good practice; never assume that a complete system reset was done between debugging sessions.

    // Disable, Reset, and Enable uDMA and then wait for the peripheral to be ready for access.
    ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_UDMA);
    ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_UDMA);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
    while(!(ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_UDMA)));

    // Disable, Reset, and Enable ADC0 and then wait for the peripheral to be ready for access.
    ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_ADC0);
    ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_ADC0);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
    while(!(ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_ADC0)));

    // Disable, Reset, and Enable Timer 0A and then wait for the peripheral to be ready for access.
    ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_TIMER0);
    ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_TIMER0);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
    while(!(ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_TIMER0)));

    // Disable, Reset, and Enable GPIO Port E and then wait for the peripheral to be ready for access.
    // We want to sample ADC from Pin PE_3
    ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_GPIOE);
    ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOE);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
    while(!(ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOE)));

    // Disable, Reset, and Enable GPIO Port N and then wait for the peripheral to be ready for access.
    // We want to toggle PN_0 every time the ADC DMA ISR handler is invoked.
    ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_GPION);
    ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_GPION);
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
    while(!(ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_GPION)));

    // PN_0 LED Toggle (Uncomment if you're going to test the LED toggle/sampling rate)
    //ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_0);
    //ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, ui8Toggle);

    /////////////////////////////////////////////////
    ////////////// uDMA Init ////////////////////////

    //Enables the uDMA controller for use.
    ROM_uDMAEnable();

    // Set uDMA Control Table Address
    ROM_uDMAControlBaseSet(ucControlTable);

    // Assign the channel 17 for ADC0 Sequencer 3 for ADC IN
    ROM_uDMAChannelAssign(UDMA_CH17_ADC0_3);

    // Put the attributes in a known state.  These should already be disabled by default.
    ROM_uDMAChannelAttributeDisable(UDMA_CH17_ADC0_3, UDMA_ATTR_ALL);

    // Set the USEBURST attribute. This is somewhat more efficient bus usage than the default which allows single or burst transfers.
    ROM_uDMAChannelAttributeEnable(UDMA_CH17_ADC0_3, UDMA_ATTR_USEBURST);

    // Configure the control parameters for the primary control structure for DMA.
    // ADC FIFO (Src) DOES NOT INCREMENT, YA BUFFOON! Arbitration size: 1
    ROM_uDMAChannelControlSet(UDMA_CH17_ADC0_3 | UDMA_PRI_SELECT,
    UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_32 | UDMA_NEXT_USEBURST |
    UDMA_ARB_1);

    ROM_uDMAChannelControlSet(UDMA_CH17_ADC0_3 | UDMA_ALT_SELECT,
    UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_32 | UDMA_NEXT_USEBURST |
    UDMA_ARB_1);

    // Set up the transfer parameters for the primary control structure.
    // The mode is set to Ping-Pong, TransferSize: 1024
    uDMAChannelTransferSet(UDMA_CH17_ADC0_3 | UDMA_PRI_SELECT,
                           UDMA_MODE_PINGPONG,
                           (void *) (ADC0_BASE + ADC_O_SSFIFO3),
                           g_ulADCValues_A,
                           NUM_DMA_TRANSFERS);

    ROM_uDMAChannelTransferSet(UDMA_CH17_ADC0_3 | UDMA_ALT_SELECT,
                           UDMA_MODE_PINGPONG,
                           (void *) (ADC0_BASE + ADC_O_SSFIFO3),
                           g_ulADCValues_B,
                           NUM_DMA_TRANSFERS);

    // This function enables a specific uDMA channel for use.  This function must be used to enable a channel before it can be used to perform a uDMA transfer.
    // When a uDMA transfer is completed, the channel is automatically disabled by the uDMA controller.  Therefore, this function should be called prior to
    // starting up any new transfer.
    ROM_uDMAChannelEnable(UDMA_CH17_ADC0_3);

    /////////////////////////////////////////////////
    ////////////// ADC0SS3 Init /////////////////////

    // Configure the analog ADC function for Pin PE_3.
    ROM_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_3);

    // Configure the ADC to use PLL at 480 MHz divided by 15 to get the maximum ADC clock of 32 MHz. This gives 1MSPS Maximum Sampling Rate?
    ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, 15);

    // Set External ADC Reference (VREFA+). BE AWARE TO SET TO INTERNAL IF YOU HAVE NO EXTERNAL REFERENCE!
    ROM_ADCReferenceSet(ADC0_BASE,ADC_REF_EXT_3V);

    // Good practice to disable the sequence before configuring it
    ROM_ADCSequenceDisable(ADC0_BASE, DMA_ADC_SEQUENCER);

    // Configure ADC to be triggered from Timer
    ROM_ADCSequenceConfigure(ADC0_BASE, DMA_ADC_SEQUENCER, ADC_TRIGGER_TIMER, 0 /*Priority*/);

    // Configure steps on sequence.  Sample channels in single-ended mode (default) and configure the interrupt flag after last conversion
    ROM_ADCSequenceStepConfigure(ADC0_BASE, DMA_ADC_SEQUENCER, 0, ADC_CTL_CH0/*PE3*/ | ADC_CTL_IE | ADC_CTL_END);

    // Enable ADC Sequence 0 Interrupt on the interrupt controller (NVIC).
    ROM_IntEnable(INT_ADC0SS3);

    // This function enables the indicated ADC interrupt sources.  Only the sources that are enabled can be reflected to the processor interrupt;
    // disabled sources have no effect on the processor.
    ROM_ADCIntEnableEx(ADC0_BASE, ADC_INT_DMA_SS3);

    // Since ADC0 sample sequence 3 is now configured, it must be enabled.
    ROM_ADCSequenceEnable(ADC0_BASE, DMA_ADC_SEQUENCER);

    /////////////////////////////////////////////////
    ////////////// Timer0A Init /////////////////////

    // Configure Timer0 to be Periodic
    ROM_TimerConfigure(TIMER0_BASE, TIMER_CFG_PERIODIC);

    // Load Timer0_A with Sampling Freq. interrupt speed.
    // We do (SamplingFreq. - 1) because the timer fires on zero.
    ROM_TimerLoadSet(TIMER0_BASE, TIMER_A, g_ui32SysClock / (g_uiSamplingFreq - 1));

    // Enable Timer 0 to trigger ADC0SS3 when it's load value is met
    TimerControlTrigger(TIMER0_BASE, TIMER_A, true);

    // Enable the Timer events that can cause an ADC trigger event.
    TimerADCEventSet(TIMER0_BASE, TIMER_ADC_TIMEOUT_A);

    return 1;
}

bool DMA_Sample_Start(uint16_t samples)
{
    if (_sampling)
        return true;

    // Initialize the Sample Stop Sequence flag
    g_ui8ADC_DMA_Sample_Stop = 0;

    // Reset g_ucDataReady flag so next Main() loop doesn't re-use old ADC data
    g_ucDataReady = 0;

    _sampling = true;

    // Set samples
    _samples = samples;

    // Un-Pend ADC0SS3's Interrupt from the interrupt controller, just in case.
    ROM_IntPendClear(INT_ADC0SS3);

    // Load Timer0_A with Sampling Freq. interrupt speed
    ROM_TimerLoadSet(TIMER0_BASE, TIMER_A, g_ui32SysClock / (g_uiSamplingFreq - 1));

    // Enable Timer 0 to trigger ADC0SS3 when it's load value is met.
    TimerControlTrigger(TIMER0_BASE, TIMER_A, true);

    // Enable the Timer events that can cause an ADC trigger event.
    TimerADCEventSet(TIMER0_BASE, TIMER_ADC_TIMEOUT_A);

    ROM_uDMAChannelDisable(UDMA_CH17_ADC0_3);


    ROM_uDMAChannelTransferSet(UDMA_CH17_ADC0_3 | UDMA_PRI_SELECT,
    UDMA_MODE_PINGPONG,
                               (void *) (ADC0_BASE + ADC_O_SSFIFO3),
                               g_ulADCValues_A,
                               NUM_DMA_TRANSFERS);
    ROM_uDMAChannelTransferSet(UDMA_CH17_ADC0_3 | UDMA_ALT_SELECT,
    UDMA_MODE_PINGPONG,
                               (void *) (ADC0_BASE + ADC_O_SSFIFO3),
                               g_ulADCValues_B,
                               NUM_DMA_TRANSFERS);

    // Enable the ADC0 Sequence 3 channel for ADC IN.
    ROM_uDMAChannelEnable(UDMA_CH17_ADC0_3);

    // Enable ADC Sequence 0 Interrupt on the interrupt controller (NVIC).
    ROM_IntEnable(INT_ADC0SS3);

    // This function enables the indicated ADC interrupt sources.
    // Only the sources that are enabled can be reflected to the processor interrupt;
    // disabled sources have no effect on the processor.
    ROM_ADCIntEnableEx(ADC0_BASE, ADC_INT_DMA_SS3);

    // Enables DMA requests to be generated based on the FIFO level of ADC0 sample sequencer 3.
    ADCSequenceDMAEnable(ADC0_BASE, DMA_ADC_SEQUENCER);

    // Enable the ADC Sequencer to sample on Timer Trigger
    ROM_ADCSequenceEnable(ADC0_BASE, DMA_ADC_SEQUENCER);

    // Enable Timer0_A to sample ADC!!! THIS SHOULD START ADC SAMPLING
    ROM_TimerEnable(TIMER0_BASE, TIMER_A);

    return true;
}

void ADC3IntHandler(void){

    static volatile uint16_t ui16inc = 0; // integrate/decimate counter, we post a new result when ui16inc = 255
    static volatile long accumulatorA=0L; // Heres where we integrate the ADC samples
    static volatile long accumulatorB=0L; // Heres where we integrate the ADC samples

    // Accumulator Variables for 'Ping' and 'Pong' Buffers,
    // Is finally copied into g_f32DecimatedArray[]
    volatile uint32_t resultA = 0;
    volatile uint32_t resultB = 0;

    ROM_ADCIntClear(ADC0_BASE, DMA_ADC_SEQUENCER);

    ADCIntClearEx(ADC0_BASE, ADC_INT_DMA_SS3);

    volatile uint32_t ui32Mode;

    // Toggle PN_0 LED, Used for verifying Sample Rate via Oscope or Freq.Counter
    //ui8Toggle = !ui8Toggle;
    //ROM_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, ui8Toggle);

    // Grab the mode
    ui32Mode = ROM_uDMAChannelModeGet(UDMA_CH17_ADC0_3 | UDMA_PRI_SELECT);

    // We have Data in Ping Buffer
    if (ui32Mode == UDMA_MODE_STOP)
    {
        // We have 256 samples in Ping Buffer, so Accumulate
        for (uint16_t i=0; i<256; i++){
            accumulatorA += g_ulADCValues_A[i];
        }

        // Decimate
        resultA = accumulatorA >> 4; // Right-Shift FOUR Virtual Bits to perform the divide operation

        // Save Result, increment the g_f32DecimatedArray index
        g_f32DecimatedArray[ui16inc++] = resultA;

        // Dump accumulator
        accumulatorA = 0L;

        // Setup a new transfer for 'Ping' Buffer
        ROM_uDMAChannelTransferSet(UDMA_CH17_ADC0_3 | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG,
                                   (void *) (ADC0_BASE + ADC_O_SSFIFO3),
                                   g_ulADCValues_A,
                                   NUM_DMA_TRANSFERS);
        // Enable the uDMA Channel
        ROM_uDMAChannelEnable(UDMA_CH17_ADC0_3);
    }

    ui32Mode = ROM_uDMAChannelModeGet(UDMA_CH17_ADC0_3 | UDMA_ALT_SELECT);

    // We have Data in Pong Buffer
    if (ui32Mode == UDMA_MODE_STOP)
    {
        // We have 256 samples in Pong Buffer, so Accumulate
        for (uint16_t i=0; i<256; i++){
            accumulatorB += g_ulADCValues_B[i];
        }

        // Decimate
        resultB = accumulatorB >> 4; // Right-Shift FOUR Virtual Bits to perform the divide operation

        // Save Result, increment the g_f32DecimatedArray[] index
        g_f32DecimatedArray[ui16inc++] = resultB;

        // Dump accumulator
        accumulatorB = 0L;

        // Setup a new transfer for 'Pong' Buffer
        ROM_uDMAChannelTransferSet(UDMA_CH17_ADC0_3 | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG,
                                   (void *) (ADC0_BASE + ADC_O_SSFIFO3),
                                   g_ulADCValues_B,
                                   NUM_DMA_TRANSFERS);
        // Enable the uDMA Channel
        ROM_uDMAChannelEnable(UDMA_CH17_ADC0_3);
    }

    // If we've incremented g_f32DecimatedArray[] by our number of samples, stop this handler so we may process data
    if (ui16inc == _samples)
    {
        ROM_TimerDisable(TIMER0_BASE, TIMER_A);

        ROM_TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT);

        ROM_IntPendClear(INT_ADC0SS3);

        // DISABLE DMA requests from being generated based on the FIFO level of ADC0 sample sequencer 3.
        ROM_ADCSequenceDMADisable(ADC0_BASE, DMA_ADC_SEQUENCER);

        // Get the Interrupt Status so we can clear it. Otherwise, we'll end up back in this interrupt handler
        uint32_t ui32ADCIntStatusEx = ROM_ADCIntStatusEx(ADC0_BASE, false); // Not Masked
        ADCIntClearEx(ADC0_BASE, ui32ADCIntStatusEx);

        // Reset the DMA Increment count
        ui16inc = 0;

        _sampling = 0;

        // Signal that we have new data to be processed
        g_ucDataReady = 1;
    }

}

Please note that this example includes integration and decimation of ADC samples, essentially allowing a finer granularity of ADC resolution (Basically, sample at a greater rate than needed, creating a virtual-resolution for sampled data)

Feel free to ask away, but this should at the very least get you going. Cheers!