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RM46L852: power sequencing during startup

Needhu Gunasegaran
Intellectual 2890 points
Part Number: RM46L852


Team,

Could you please answer my customer question,

I would need some help with the power sequencing of the RM46L852PGE controller.

 The statement in the datasheet says that the device may be powered up in any order on the supplies. I have a colleague writing software, who managed to destroy some controllers. I am not sure, if this is not a problem caused by him during testing. But I am doing a review at the moment to see, if there is any critical point.

 

In the past, we had some contact about the power management IC TPS65381. The result from that was that a colleague from TI recommended to use an external buck regulator to supply the core voltage. I start this buck together with the ignition signal at the TPS. The result is that the TPS starts quite some milliseconds later.


(Ch1: 3V3 output of the TPS, Ch2: 1.2Volts core, Ch3: 5Volts for the ADC supply, Ch4: other ICs are connected to this 3V3, enabled by rising 3V3 from the TPS)

If one really may power up in any order, this should not be a problem. But I have to do a redesign for some other reasons. So there would be room for improvements.

Is there a risk with this sequence that is not obvious in the datasheet?

 

Another question is: If this colleague makes a mistake to switch a pin to output, which is connected to another output. Is this a problem that results in failed device? (For example a pin switched to output high that is pulled down to GND) It should not happen, but as you know… everything is possible J

 

I never managed to damage a controller by myself. So if you asked me about that, I would say that there is not a problem. So I would appreciate some advice with that. Thank you!

Thank you,

- Needhu

  • 0
    TI__Guru 59540 points

    Needhu,

    The device has a built in VMON circuit that controls the release of reset until the voltages are within a respectable range. i.e., it helps protect against issues with power rails coming to the proper level/i.e. power sequencing. This should not be a problem. 

    In the past, we had some contact about the power management IC TPS65381. The result from that was that a colleague from TI recommended to use an external buck regulator to supply the core voltage. I start this buck together with the ignition signal at the TPS. The result is that the TPS starts quite some milliseconds later.

    There is no need for an external buck regulator. For certain, the core supply from the TPS has a tolerance of +/-6% which can lead to voltages just outside of the operating range. To mitigate this we have recommended in the past to configure the core supply of the TPS65381 device to 1.23V which means the core supply would be well within the 1.2V -5/+10% range specified in the datasheet. Note that the delay in powering up the TPS is most likely a result of the ABIST and LBIST that occur at power up for the device. This is a necessary step for safety.

    Another question is: If this colleague makes a mistake to switch a pin to output, which is connected to another output. Is this a problem that results in failed device? (For example a pin switched to output high that is pulled down to GND) It should not happen, but as you know… everything is possible J

    Certainly forcing an output high when pulled to ground either directly or through a resistance can cause harm to the device. Of concern is if the resulting current violates the load spec of the IO. There is some level of margin against the spec but considering the loading impacts not only the load through the pin but also through the power rails within the device, some extreme cases can permanent damage to the device power rails if the currents including overshoot are taken into account.

    Looking at the power sequencing, I see that the 5V rail ramps much faster and sooner than all the others. Why is this not also coming from the TPS device? All of the needed rails to drive the MCU can be brought from the TPS device. In addition, you can also supply the external devices at 3.3V using the sensor supply from the TPS. There should be no need for any additional buck regulators for these additional rails. I don't have details to know if this is truly a problem or not, but I would be concerned with the ADC supply (and assumed reference) ramping so much sooner than the IO and core supplies. This can create some biasing issues and and attempts to power the device via the ADC supply pins.

    Here is a recommended hook up of the TPS to the Hercules device from an application note on the subject of TPS65381+Hercules (Interfacing TPS65381 With Hercules Microcontrollers (Rev. A))

    Note, I am also copying Scott Monroe who is the expert on the TPS/PMIC side in case he has anything to add relative to PMIC hookup.

  • 0 in reply to Chuck Davenport
    TI__Intellectual 2890 points
    Chuck,

    Please see the comments from my customer.

    I use an external low noise LDO to get the 5V for the ADC. This is because I need a good noise performance. And the TPS65381 is simply a too noisy IC. It generates high noise in the audible range and this is what I am working with. So… different source for the 5V. With that solution I get only 2 or 3 digits peak to peak on the 12bit ADC and that is very good in my opinion.

    I take the core supply from a buck regulator simply because of power dissipation. That was checked with Mr.Monroe. I also take the 6V from a different regulator, because the hysteretic control of the TPS-Buck makes unacceptable noise in my application. I cannot use the VSOUT1; 100mA minimum current limit is too low. Maybe I do not understand something correctly. And there are some decisions open that influence the current needed by the 3V3…

    I think that I will couple all enable voltages to the 3V3 from the PMIC. That would mean the 3V3 is starting and the other voltages come up with a delay of a few milliseconds. (Just like Ch4 on my picture below). This would also solve the issue with the 5V.

    Thank you for the good description. I will have a look on the core supply voltage, very useful hint!

    Thanks,
    Needhu
  • 0 in reply to Needhu Gunasegaran
    TI__Guru 59540 points
    Needhu,

    Thanks for the additional details and all are valid reasons for deviation from our normal solutions. I agree that it would be better to gate the other supplies by the 3.3V supply PG signal if at all possible but I do not have a great response on why the behavior that has been observed has been occurring . The only possible reason could be the 5V supply causing some reverse biasing via the ADC supply and references but I am not aware of any prior issues with it.
  • 0 in reply to Chuck Davenport
    TI__Guru 59540 points
    Please let me know if the coupling of the enables to the 3.3 V supply takes care of the problem or not. This would be useful information for others on the Forum.