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CCS/TM4C1294NCPDT: uDMA bus errors when using EMAC

Part Number: TM4C1294NCPDT

Tool/software: Code Composer Studio

Hi,

Is there any way to set priorities for EMAC DMA and uDMA, or to avoid bus errors on uDMA when using EMAC DMA?

I need to send data constantly using uDMA (memory->SSI1) in ping-pong mode, for 28ms, then transmission stops for about 5ms. Then cycle repeats.

If Ethernet packet arrives during uDMA transmission it causes uDMA bus error - uDMAErrorHandler is called and uDMAErrorStatusGet returns 1. In result, ping-pong transmission is stopped (and this must be avoided, constant data flow must be maintained).

ETH may have lower priority in this case and data copy can be postponed if it's neccessary.

I'm not using RTOS, using lwIP stack with almost default configuration (more buffers added to ETH).

Any ideas how to get rid of uDMA bus errors?

Thans!

My configuration below:

#define SYSTICK_INT_PRIORITY    0x80
#define ETHERNET_INT_PRIORITY   0xC0
#define SSI1_INT_PRIORITY       0x00
 
int main(){ 
(...)
MAP_IntPrioritySet(INT_EMAC0, ETHERNET_INT_PRIORITY);
MAP_IntPrioritySet(FAULT_SYSTICK, SYSTICK_INT_PRIORITY);
MAP_IntPrioritySet(INT_SSI1, SSI1_INT_PRIORITY);

uDMAChannelAttributeDisable(UDMA_CHANNEL_SSI1TX,
                            UDMA_ATTR_ALTSELECT |
                            UDMA_ATTR_HIGH_PRIORITY |
                            UDMA_ATTR_REQMASK);

uDMAChannelControlSet(UDMA_CHANNEL_SSI1TX | UDMA_PRI_SELECT,
                      UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE |
                      UDMA_ARB_4);

uDMAChannelControlSet(UDMA_CHANNEL_SSI1TX | UDMA_ALT_SELECT,
                      UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE |
                      UDMA_ARB_4);

SSIIntEnable(SSI1_BASE, SSI_DMATX);
(... channel transfer set, uDMAChannelEnable...)
IntEnable(INT_SSI1);

}

lwIPInit()
{
 MAP_EMACPHYConfigSet(EMAC0_BASE, EMAC_PHY_CONFIG);

    //
    // Initialize the MAC and set the DMA mode.
    //
    MAP_EMACInit(EMAC0_BASE, ui32SysClkHz,
                 EMAC_BCONFIG_DMA_PRIO_WEIGHT_1 | EMAC_BCONFIG_MIXED_BURST | EMAC_BCONFIG_PRIORITY_FIXED,
                 1, 1, 0); //<<<<---- This was set default without PRIO_WEIGHT param and with 4,4,0. Result was the same.

    //
    // Set MAC configuration options.
    //
    MAP_EMACConfigSet(EMAC0_BASE, (EMAC_CONFIG_FULL_DUPLEX |
                                   EMAC_CONFIG_CHECKSUM_OFFLOAD |
                                   EMAC_CONFIG_7BYTE_PREAMBLE |
                                   EMAC_CONFIG_IF_GAP_96BITS |
                                   EMAC_CONFIG_USE_MACADDR0 |
                                   EMAC_CONFIG_SA_FROM_DESCRIPTOR |
                                   EMAC_CONFIG_BO_LIMIT_1024),
                      (EMAC_MODE_RX_STORE_FORWARD |
                       EMAC_MODE_TX_STORE_FORWARD |
                       EMAC_MODE_TX_THRESHOLD_64_BYTES |
                       EMAC_MODE_RX_THRESHOLD_64_BYTES), 0);
}

  • I'm sorry, topic can be closed.

    Reason was stack overflow. It was set to 512 bytes.

    In Eth read function I allocated 1,5kB buffer on stack (for testing purposes), and sometimes it was overwritting DMA Ping-Pong configuration structure. So in one of following cycles it caused DMA Bus Error because of invalid address.

    Thanks!
    MJ