TMS570LC4357: External SDRAM issue with EMIF

Hello Swapnil,

I have forwarded to one of our EMIF experts so they can address the results that you are seeing. They should be in contact soon.

Hello Swapnil,

Any other changes in code and project settings? For example, cache enabled, etc. I will do a test tomorrow, then come back to you.

Hi,

Thanks for you reply. All the settings are same. newTempVar is simply commented out. I am using the guide from Hercules examples for EMIF SDRAM setup with appropriate settings for my sdram.

This is the datasheet for my SDRAM.  http://www.issi.com/WW/pdf/42-45S16400J.pdf 

I am using IS45S16400J-7BLA2 Version (-7) for timing if you need to check that.

Besides that, I am attaching my project which I am using for this test. 

2705.SDRAM_20171214.zip

Thanks for you response!

Swapnil 

Hello Swapnil,

I did a test with your modified code, and the value from the three locations in SDRAM are correct. This is my test screen, and the test was repeated hundred times, and the num_errors is 0. Did you change the EMIF settings?

Hi,

I haven't changed my code. And on my end it does not work. if I brakpoint through three lines where I am writing to memory, this is what i see after each line on memory browser.

After first line, 

0x80000000      A500

0x80000002      0000

0x80000004      0000

After second line,

0x80000000      0000

0x80000002      B500

0x80000004      0000

and after third line, 

0x80000000      0000

0x80000002      0000

0x80000004      C500

And then when I do readback, it results in an error. Do you know what could cause that?

Thanks 

Tested again with your project on TI TMS570LC43x HDK, it works fine. I could not re-produce the problem.

In the first post, you said that you read the value back without any problem, and you got the problem after changing the code. What are the differences between 2 projects?

Hi,

Thanks for your help. Would you be able to upload the code that you used to test on HDK?

and the difference between two code was only assigning 0 to temporary variable (it was not used anywhere).
But even when we did that, looking at memory location was always same as how I described in my earlier post.

on the datasheet for SDRAM it says CLK frequency is 133 MHz for CAS Latency = 2. Does this frequency have to match the VLCK3 frequency of the CPU? Our VLCK3 frequency is set to 75 MHz. Could that cause problems?

Thanks

Hello Swapnil,

I used the project you posted.
You can use any valid frequency for EMIF (<100MHz, defined in datasheet). Please probe the EMIF signals on your board.

Hi,

Thanks for you reply. We tried this code on our HDK and it worked fine.

The one thing we noticed was on the schematics for HDK pin D10, D11, and D13 are labelled as ETMDATA[15]/EMIF_nDQM[0], ETMDATA[14]/EMIF_nDQM[0] and ETMDATA[12]/EMIF_BA[0]

Our custom board is wired to SDRAM based on this configuration. But as per the TRM and Datasheet for TPS570LC43xx, It should be E10, E11, and E13. They are labelled as ETMDATA[15]/EMIF_nDQM[0], ETMDATA[14]/EMIF_nDQM[0] and ETMDATA[12]/EMIF_BA[0] on TRM, datasheet as well as HALCOGen. 

Is there an error in the schematics for HDK? 

I am looking at following release of schematics from 

Thanks, 

TMDX570LC43HDK Schematic Design File (Rev. A)

ZIP

761

20 Aug 2015

401

Hello Swapnil,

They should be E10, E11, and E13. Please use the ball assignment in datasheet. This is the EMIF signals used on HDK:

Hi,

We made an error and assumed D10, D11 and D13 were same as E10, E11, and E13 since they had same label on the schematics for HDK.

Is there way to still use EMIF drivers with those pins? any help would be apperciated!

Thanks.

Hello Swapnil,

It won't work properly without the PCB modification.