TMS570LC4357: Behaviour when PLL slip detects a failure while OSCIN clock source is disabled

Hello Gael,

If the clock detector is disabled, it will unconditionally switch GCM clock source 0 back to the oscillator, so care should be taken to insure that the oscillator is good before disabling the clock detector.

If the oscillator fails before the PLL slip is detected, the LPO HF is sourced to both GCM source 0 and 1.

PLL slip means that the PLL is not locked properly: PLL is too fast or too slow. The oscillator failure also causes PLL slip.

Hi,

I'm sorry if my question was not clear, but it's more related to the CPU behaviour if the main oscillator clock source is disabled.

In startup phase,:

- the PLL is setup and locked.

- the PLL is selected as the source for clock domains

- clock detector is disabled (to avoid a failure due to oscillator disabling one step below)

- main oscillator (clock source 0) is disabled in CSDIS register

First question: can the main oscillator (clock source 0) be disabled in the CSDIS register if the PLL1 is planned to be used for the clock domains?

Now - assuming we can disable the main oscillator and use the PLL1 - the CPU runs on the PLL1 clock source and PLL slip is enabled.

My question is: in those conditions, if a PLL slip is detected:

1) is the PLL1 source switched to the main oscillator (which is disabled)? (in that case, the CPU is halted)

2) is the PLL1 source switched to the main oscillator which is automatically enabled by the clock logic? (in that case the CPU continues on the main oscillator)

3) is the PLL1 source switched to the HF LPO?

Best regards,

Gael

Hi,

I found information on the TMS570LC4357 Silicon B errata document, which includes GCM#59.
In the text, we can find that if the PLL clock source is enabled, then the main oscillator must not be disabled.

This answers all previous questions.

Still, I made some experiments:
- GCLK, HCLK, VCLK, VCLK2 and VCLK3 clock source is set to PLL1
- RTI clock source is set to VCLK (default value) which is derived from PLL1
- VCLKA1, VCLKA2 and VCLKA4 clock domains are disabled (CDDIS = 0x00000830)
- Clock detector is disabled (CLKTEST = 0x010A0000)
- Global Status register indicates no error (GLBSTAT = 0x00000000)
- I want to disable all unused clock sources: LPO LF, LPO HF, EXTCLKIN1, EXTCLKIN2, PLL2 by writing CSDISSET with 0x000000FC
- In an infinite loop I poll CSVSTAT register but it remains to value 0x000009B, which indicates that OSCIN, PLL1, EXTCLKIN1, LF LPO and EXTCLKIN2 clock sources are valid. I was expecting that only OSCIN and PLL1 would be indicated as valid.

How do you explain that EXTCLKIN1, EXTCLKIN2 and LF LPO clock sources still remain valid in CSVSTAT register?

Best regards,
Gael

Hello Gael,

1. The PLL source is always OSCIN.
2. GCM source can be PLL1/2, OSCIN, LPO, and external clocks
3. If PLL is the GCM clock source, and clock detector is disabled, and OSC is also disabled, the PLL doesn't have clock source, and GCM will not use LPO as the source since the clock detector is disabled. So the CPU will stop running.
4. If PLL slip occurs, the slip detector will switch GCM clock source to OSCIN, but your OSCIN is disabled, so GCM doesn't have clock source.

Hello Gael,

The clock source #3, #4, and #7 are valid in default, and are always usable. Disabling the clock source #3/4/7 will not affect the value in CSVSTAT.

Hello,

I'm not sure to understand what you just wrote: do the clock sources #3, #4 and #7:

A) can be disabled, but their status is not reflected in CSVSTAT register?

or

B) can not be disabled (you wrote "are always usable")?

If A) is true, then why does my debugger loses control of the CPU when I try to disable the bias current of the LPO (set BIAS_EN to 0 in LPOMONCTL register)?

If B) is true, then why does the TRM mention that it is feasible in chapter 2.4.1.1: "Each clock source can be independently enabled or disabled using the set of Clock Source Disable registers" and in chapter 14.4.5.2 (for LF LPO clock source): "Similarly, the LPO LF clock is reset by setting CSDIS.4 [...]. The LF LPO disables several LF LPO cycles after CSDIS is set." ?

Thanks,

Gael

Hello Gael,

From the TRM statement, those clock sources can be enabled and disabled using CSDIS register. But writing "1" to those bits in CSDIS will not affect the default value in this register.

Yes that's certainly an error in the TRM, but the code I've written performed correctly the accesses to the registers that SET or CLEAR the Clock Sources (CSDISSET and CSDISCLR).

Do you have answers for my previous questions? What did you mean by "Disabling the clock source #3/4/7 will not affect the value in CSVSTAT"? An why are they different from the other clock sources that can be disabled? My comprehension of the CSVSTAT register also was that if a clock source is effectively disabled, this clock source should be indicated as not valid in the CSVSTAT, am I wrong on that?

If this is a correct behaviour specifically for clock source #3, #4 and #7, then it should be documented because this is not compliant to the documentation.

Best regards,

Hello QJ,

For external clocks, Ok, I understand. But what about Clock Source #4 (LF LPO)? When I disable it via CSDISSET register, and then I try to disable the bias current of the LPO (set BIAS_EN to 0 in LPOMONCTL register), the CPU freeze via the debugger.
Can you explain to me why?

Best regards,