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TMS570LS0432: Generate a Supervisor Call Exception

Andy Bolanos
Prodigy 40 points
Part Number: TMS570LS0432
Other Parts Discussed in Thread: HALCOGEN

Hello,

I'm part of software verification project that uses a Hercules Microprocessor as part of our job we need to verify that the exception handler table is hit by the software in any case that each of these ones is triggered. According to the TRM SPNU517b, the table is like this:

0x00000000 Reset

0x00000004 Undefined instruction

0x00000008 Software Interrupt

0x0000000C Prefetch Abort

0x00000010 Data Abort

0x00000014 Reserved for future use

0x00000018 IRQ

0x0000001C FIQ

Because of the way the software is being developed we received updates/changes to the software, so initially we look at the disassembly code in CCS for an SVC instruction set the PC in there let the program run the verify that the address 0x00000008 was hit however with the latest version of the software there are not SVC instructions in the disassembly code and we don't have a clear idea how to generate the Supervisor exception, if anyone can explain how this could be possible I will appreciate it.

Kind regards.

Note: we are not allowed to modify the code in order to do the verification.

  • 0
    TI__Guru**** 196776 points
    Hello Andy,

    The freeRTOS from HALCoGen provides a example code for SWI handler:

    Code in sys_intvec.asm:
    ;-------------------------------------------------------------------------------
    ; interrupt vectors

    resetEntry
    b _c_int00
    undefEntry
    b undefEntry
    b vPortSWI
    prefetchEntry
    b prefetchEntry
    b _dabort
    b phantomInterrupt
    ldr pc,[pc,#-0x1b0]
    ldr pc,[pc,#-0x1b0]


    Code in os_portasm.asm:
    ;-------------------------------------------------------------------------------
    ; SWI Handler, interface to Protected Mode Functions

    .def vPortSWI
    .asmfunc
    vPortSWI
    stmfd sp!, {r11,r12,lr}
    mrs r12, spsr
    ands r12, r12, #0x20
    ldrbne r12, [lr, #-2]
    ldrbeq r12, [lr, #-4]
    ldr r14, table
    ldr r12, [r14, r12, lsl #2]
    blx r12
    ldmfd sp!, {r11,r12,pc}^

    table
    .word jumpTable

    jumpTable
    .word swiPortYield ; 0 - vPortYieldProcessor
    .word swiRaisePrivilege ; 1 - Raise Priviledge
    .word swiPortEnterCritical ; 2 - vPortEnterCritical
    .word swiPortExitCritical ; 3 - vPortExitCritical
    .word swiPortTaskUsesFPU ; 4 - vPortTaskUsesFPU
    .word swiPortDisableInterrupts ; 5 - vPortDisableInterrupts
    .word swiPortEnableInterrupts ; 6 - vPortEnableInterrupts
    .endasmfunc