RM57L843: RAM ECC Question

Hello Dmitri,

First, to be clear, we are discussing only the L2 SRAM not the Cache RAM.

The L2 SRAM, is protected by ECC by default. i.e., this means that ECC is enabled by default out of reset. The ECC logic resides in two places. It is in the CPU and it is in the L2 SRAM Wrapper.

If there is a fault (single bit error) detected in the data that is sent to the CPU, it will be corrected by the ECC logic in the CPU. In this case, the content of the L2 SRAM location that has the fault remains unchanged meaning that the same single bit fault will be present when the same location is read again. The fact that these faults remain will then increase the likelihood/risk of another fault occurring in the same 64-bit space and result in an un-correctable double bit error.

For this reason, the device has implemented a couple of ways that the actual data within the L2 SRAM will be corrected if the fault is a transient fault. First, in the case of a write to a 32 bit location, there is a read-modify-write (RMW) operation that takes place for the entire 64 bits of data to which the ECC value applies. i.e., if there is a single bit error found in additional 32-bits that are "not being written" it will be corrected and subsequently written back with a corrected content clearing the transient fault. Secondly, if memory scrubbing is enabled, it forces the RMW cycle even on pure reads from the L2 SRAM resulting in single bit errors being corrected on the fly in L2 SRAM. The combination of these operations reduces the probability of double bit faults due to the re-writing of data into their respective SRAM locations with the corrected bit flips/transient faults.

To be more direct in answering your initial question:

Dmitri Zakharevski59 said:

If I understand the technical reference correctly by default, the RAM ECC will not automatically correct single bit errors unless enabled by setting the Memory Scrubbing Enable (MSE) bit in the L2RAMW Module Control Register (RAMCTRL)

Single bit errors are always corrected in data before being supplied to the CPU; however, physical single bit errors in memory are only corrected during RMW operations and when memory scrubbing is enabled.

For your second half of the question:

Dmitri Zakharevski59 said:

and will not signal detected errors unless enabled through CPUWSC: CPU Write SERR Capture bit.

You are correct. In many cases, applications do not care about single bit errors since they are corrected on the fly and have no impact on the safe operation of the application. In these cases, it is not required or necessary to monitor single bit faults or the correction of them. For this reason, notification of them is optional. In order to export single bit error notifications to the ESM, this feature must be enabled via the CPUWSC bit field. LIkewise, the EEMMS bit field should be asserted to enable ESM notification of single bit error correction resulting from the memory scrubbing feature.

It is worth noting that, all double bit error notifications will occur and will result in, at minimum, a data abort exception for the CPU.