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RM57L84x I2C can't output SCL

Other Parts Discussed in Thread: HALCOGEN

hi,

I'm using the  RM57L84x as the I2C master, communicating with an I2C peripheral that operates at 100kHz.

it works well at most of time,but occasionally the RM57L84x can‘t output SCL(clk)。When this phenomenon

appears,I check  the Tx data has been already loaded into  the Tx register I2CDXR。Power off the RM57L84x

for a while, the communication turn to normal. My i2c driver code is generated by HALCoGen 04.06.01。

the code is as follows:

uint8 writeDataToRTC(uint8 addr,uint8 cnt, uint8* data)

{   

    uint32 delay = 0;

    ///////////////////////////////////////////////////////////////     //        Master Transfer Functionality                      //     ///////////////////////////////////////////////////////////////

    /* Configure address of Slave to talk to */ 

    i2cSetSlaveAdd(i2cREG1, RTC_ADDRESS);

    /* Set direction to Transmitter */    

    /* Note: Optional - It is done in Init */    

    i2cSetDirection(i2cREG1, I2C_TRANSMITTER);

    /* Configure Data count */ 

    /* Data Count + 1 ( Word Address) */ 

    i2cSetCount(i2cREG1, cnt + 1);

    /* Set mode as Master */ 

    i2cSetMode(i2cREG1, I2C_MASTER);

    /* Set Stop after programmed Count */ 

    i2cSetStop(i2cREG1);

    /* Transmit Start Condition */ 

    i2cSetStart(i2cREG1);

    /* Send the Word Address */ 

    i2cSendByte(i2cREG1, addr);

    /* Tranmit DATA_COUNT number of data in Polling mode */ 

    i2cSend(i2cREG1, cnt, data);

    /* Wait until Bus Busy is cleared */    

    while(i2cIsBusBusy(i2cREG1) == true);

    /* Wait until Stop is detected */    

    while(i2cIsStopDetected(i2cREG1) == 0);

    /* Clear the Stop condition */   

    i2cClearSCD(i2cREG1);

    /* Simple Dealya before starting Next Block */   

    /* Depends on how quick the Slave gets ready */    

    for(delay=0; delay<100000; delay++);

    return 1;

}

 

  • Hello User,

    Have you checked the source of the SCL low period. In most I2C applications, the slave can force clock extension and hold the SCL low so that the master cannot send anymore data until it is ready to receive it. This is a natural way for the slave to be able to gate information coming to it until it is ready. One way to test this is to disconnect the slave during one of these periods and see if the master begins toggling SCL once again.