TMS570LS3137: DFSR and ESM

Jordan,

The DFSR is a CPU register within the CP15 register block. It is CPU accessible and can be read upon the CPU issuing an exception. The events covered by the DFSR are outlined in the Cortex-R4F TRM on the ARM website at this location: infocenter.arm.com/.../index.jsp. Specifically, you will find information about the DFSR in section 4.2.18.

Generally speaking, the events outlined as applicable to the DFSR are not covered by the ESM since they are CPU exceptions and would require an abort handler to determine the details of the abort according to the DFSR including the type of abort and the source. The abort handler could, theoretically assert the nERROR pin via SW if needed for their safety or system concept.

Hello Jordon:

The ARM TRM gives the DFSR incodings as shown in the table below.

For the reading 0x008 it corresponds to a Precise External Abort.

For the value of 0x80D indicates a permission violation from an AXI slave error.

Below is the DFSR register definition which can be interpreted together with the table above. The status is a combination of bits12, 10 and 3:0. The table above defines the meaning of bits 10 and 3:0. Bit 12 indicates either a read if 0 and write if 0.

For further debug, they can take a look at the Fault Status Address register and determine what address the code was accessing that caused the violations.