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TMS570LC4357: EMAC RX interrupts hangs when host sent too many UDP packages

Kamil Zorychta
Prodigy 20 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hello,

I'm working with a TMS570LC4357 microcontroller (Hercules LaunchPad Development Kit TMS570LC43x).

I have ran LwIP demo with success, HTTP server is working.

Board is connected to LAN and has configured static IP address. Communication is performed between board (192.168.0.101) and PC (static IP 192.168.0.102).

I have got issue with receiving too many UDP packages (200 bytes payload). 

What I observe:

  1. when host sends packages with 10ms delays between them, everything works well,
  2. when host sends packages one by one,  as fast it can, board hangs up in Rx interrupt after about 70 packages.

After hang up, I pressed pause in debugger and I see that variable rxch->active_head is set to NULL.

Software has not any mechanism to prevent getting data from NULL pointer and stay in infinite loop.

I have added "if guard", this help that application does not hang up but EMAC Rx interrupt is no triggered longer.

This seems to be hardware capability issue.

Questions:

  1. Is any way to prevent such situation?
  2. Is it possible to ignore incoming packages if microcontroller cannot handle them?

Best regards,

Kamil Zorychta

,Regarding EMAC driver, I struggling with hanging up RX interrupt when host sending too many packages.
  • 0
    TI__Guru**** 198766 points
    Hello Kamil,

    The EMAC could not receive the new packet since it was out of FIFO space. The FIFO overrun condition occurs when your destination is not receiving packets as fast as the host (PC) is transmitting them. So you can look at either improving the performance of the system (more FIFO space, using DMA) or try to limit the throughput from the host side. Which interrupt flag is set when the failure occurs?
  • 0 in reply to QJ Wang
    Prodigy 20 points
    Hello QJ Wang,

    Thank you for your replay. You confirmed my observations.
    Software stay in EMAC Rx Handler, so EMAC Rx flag is set (EMACCore0RxIsr: Channel 79).
    I see that the following registers were set:
    - RXSOFOVERRUNS 0x00000000
    - RXMOFOVERRUNS 0x00000077
    - RXDMAOVERRUNS 0x00000077

    So it is definitely performance issue.
    I have got question related with receiving packages, is it possible to ignore incoming package when FIFO is full?
    I would like to prevent occurring NULL pointer in Rx queue.

    Best regards,
    Kamil Zorychta
  • 0 in reply to Kamil Zorychta
    TI__Guru**** 198766 points
    The EMAC was unable to receive it because it did not have the resources to receive it: cell FIFO full or no DMA buffer available.
  • 0 in reply to Kamil Zorychta
    Expert 1810 points

    There is some problem on ethernet buffer chaining code described in TRM and in HalCoGen code.

    After fix it we didn't have problem to process more than 10000 UDP packets per second.

    Jiri

    e2e.ti.com/.../678879