• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 30 subscribers
  • Views 1191 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RM48L952: Problems with nested interrupts, FIQ interrupting IRQ

Thiago Esteves
Prodigy 85 points
Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN

Hi,

I can't post my code here, but I will try to explain my scenario and I'd like to ask if this is a valid scenario or not. Our project has 2 interrupts (IRQ and FIQ). The IRQ (RTI - compare 1) runs every 1 millisecond and the FIQ (RTI - compare 0) runs every 125 microseconds. The 1ms interrupt takes more than 200 us to finish its execution and it eventually uses the emulated eeprom code provided by ti (FAPI). The diagram below shows how they are related by:

The X represents the CPU processing. As you can see, sometimes the IRQ can be interrupted by the FIQ and when it occurs, the FIQ process its code, returns, but the interrupt stack related to the IRQ is corrupted and at the return of the IRQ, the system crashes. It seems to me the FIQ, for some reason, is destroying the stack saved by the IRQ.

Questions:

  • Does the FAPI support being interrupted by FIQ when it is running in the interrupt service called by an IRQ?
  • Is the approach (FIQ+IRQ) mentioned above a valid one?


PS: If I modify the code, changing the FIQ to IRQ and using the code provided by TI which allows the IRQ to be preempted by another IRQ of high priority, the problem doesn't manifest, it runs as expected.

Kind Regards,

Thiago Esteves

  • 0
    TI__Guru**** 192486 points
    Hello Thiago,

    The ARM Cortex-R4 core does not support more than one IRQ to be taken at a time. This is mainly because it has only one SPSR and one LR register. If an IRQ is interrupted by another IRQ, these CPU registers would get overwritten (corrupted) and a later restoring of the processor state would not be possible anymore. If you want to use the nested IRQs which is not recommended, your ISR handler needs to preserve the CPU general registers (SPSR, LR, etc) on the stack.

    FIQ+IRQ should work fine. Can you please try FIQ+IRQ without flash operations in your ISR? Thanks
  • 0 in reply to QJ Wang
    Prodigy 85 points

    Hello Wang,

    Thanks for the answer, I created an eeprom stub to emulate the eeprom and the results are still the same when it returns from the FIQ to the IRQ, the system loses the STACK (I can see by the code composer debug). I commented out all the FIQ code, the ISR is doing nothing. My guess is that I am missing some configuration. I am using HALCOGEN and checking the registers, it seems to me that RTI compare 0 is properly configured as FIQ and rti compare 1 is configured as IRQ. Am I missing something? I attached one image with my configuration. I changed the called function by rtiCompare0Interrupt just to avoid them to share the same function.

    KR

    Thiago Esteves

  • 0 in reply to Thiago Esteves
    Prodigy 85 points
    Hi guys,
    I solved my problem, the IRQ+FIQ really works. I was facing a stack overflow during the IRQ. The stack configured for IRQ in the HALCOGEN was too small to my project.

    Thanks a lot
    Thiago Esteves