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MIbSPI Transfer Group Sequencer operation and trigger mechansim

Pashan
Intellectual 715 points

Hello,

I find the following statement within TRM under BUFMODE bit definition of MultiBuffer RAM fields :

 

 

 

suspend single-transfer mode.

 

Suspend-to-wait until the corresponding

TXFULL flag is set (i.e. the sequencer stops at the current

buffer until new transmit data is written in the TXDATA field).

My question is: when the SEQUENCER is stopped under the above mentioned circumstance for a low priority Transfer Group, then if a higher priority TGxCTRL register's TGENA bit is set, then does the SEQUENCER starts the new recently activated Transfer Group as pointed by TGxCTRL Register TGENA bit.

I couldn't find any detailed description of when does the SEQUENCER starts a new scan of TGxCTRL register's TGENA bit.

Or, when the SEQUENCER gets triggered for a new scan after it has been stopped at a buffer due to BUFMODE bit-field setting?

Any better explanation of the MibSPI SEQUENCER will help me a lot.

Thank you.

Reagards

Pashan

 

  • 0
    TI__Genius 14205 points

    Pashan,

    Eventhough Low Priority TG( Transfer Group) is suspended, if High priority TG is triggered then High Priority TG will be serviced.
    Only under the following conditions a lower priority TG cannot be interrupted by a higher priority TG.
    1. When there is a CSHOLD or LOCK buffer, until the completion of the next buffer transfer which is a non-CSHOLD or non-LOCK buffer.
    2. An entire sequence of words transferred for a NOBRK DMA buffer.
    3. Once the last word in a TG is pre-fetched.

    Thanks!!!

     

  • 0 in reply to Prathap
    Intellectual 715 points

    Hello Prathap,

    Thank you for the answer.

    I have following question:

    1> SEQEUNCER starts scanning whenever there is a change in any of the available TGxCTRL Register's TGENA bit is changed to active state or SEQUENCER has it's own cycle of scanning period to check TG of highest priority and ACTIVE? In short, when does the SEQUENCER wakes up?

    2> Does PSTART bit-field of TGxCTRL Register have to follow any order? By this I mean, does TG0 -- PSTART has to have lower Multi-Buffer Address Index than any of the higher numbered TGxCTRL Register's PSTART bit-field? That means, does TGxCTRL PSTART Index can be in any order within the MultiBuffer RAM Index?

    Thank you.

    Regards

    Pashan

     

  • 0 in reply to Pashan
    TI__Genius 14205 points

    Hi Pashan,

    Answer to your question

    1) Two factors that Sequencer looks that is 1) Transfer group Enable 2) Is the transfer group trigger, TGTD .
    If both conditions are true then the Transfer gropus are serviced as per priority.

    2) Yes, PSTART for TG0 will have the lowest addess. Looking at TGxCTRL register it has only PSTART, PSTART of TG1 acts as END address for TG0. 
    Just wondering, what type of useage are you looking at?

    Regards
    Prathap