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MibSPI DMAxCTRL Register for Transmit as well as Receive when more than one Multi Buffer is being used

Pashan
Intellectual 715 points

Hello,

I am trying to use a DMAxCTRL Register within MibSPI to perform Transmit and Receive using 4 MutiBuffer RAM.

My SPI Message Block size is 64-Bits and MibSPI on TMS570 side is being used as SPI MASTER.

How do I use the BUFID field within DMAxCTRL to transfer SPI 64-Bit data first using DMA and then trigger the DMA Receive when all the 64-Bits have been sent out by MibSPI Master?

There is only one BUFID field within DMAxCTRL Register even though RXDMAMAP and TXDMAMAP fields are there and I needed to Trigger DMA Tx to trigger first when MultiBuffer RAM Transfer Index is at the beginning and DMA Rx to trigger only when all 64-Bits have been sent out using 4 MutiBuffer RAM entries.

Any clue about how to use the DMAxCTRL BUFID for synchronizing both DMA Tx as well as DMA Rx cycles.

Thank you.

Regards

Pashan

 

 

  • 0
    TI__Genius 13810 points

    Pashan,

    Your query has been forwarded to our expert team members, will get back to asap.

    Regards,

    Haixiao

  • 0
    TI__Genius 14205 points

    Hi Pashan,

    There was a post on the forum regarding MIBSPI DMA, please click the below link to access.

    http://e2e.ti.com/support/microcontrollers/tms570/f/312/p/63549/228727.aspx#228727

    For your requirement, you can use TG0 of length 4, for both transmit and receive. With BUFID = 3 for two DMA channels one for Tranmit and one for receive. 
    So whenever buffer3 ( 4th buffer i.e 0,1,2,3) is expty it will trigger a DMA TX request, whcih can be used to copy data to Buffer 0 to 3. Similarly when the data is received at RX buffer3( 4th buffer), it will trigger DMA request. this can be used by other DMA channel to read data from buffer 0 to 3.

    Best Regards
    Prathap

  • 0 in reply to Prathap
    Intellectual 715 points

    Hello Prathap,

    By following your last reply, can you please tell me what will be the value of BUFMODE field of 4th Multi-Buffer RAM Cell Configuration with BUFID=3, where I want to occur DMA TX and RX synchronous with BUFID=3 being TXEMPTY as well as RXFULL?

    I am yet to understand when does DMA RX gets triggered?

    Is it that whenever any MultiBUffer RAM is SPI Data Received and BUFID matches, DMA RX gets triggered?

    Thank you.

    Regards

    Pashan

     

  • 0 in reply to Pashan
    TI__Genius 14205 points

    Hi Pashan,

    If it is for simple application, where in no other TG are used you can go with BUFMODE = 111b.

    As soon as data is received( i.e. RXEMPTY = 0) in the Buffer( your case 4th buffer) as specified in the BUFID of  DMAxCTL, DMA RX request is triggered.

    Best Regards
    Prathap