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CCS/TM4C123GH6PM: Is there any boot loader example that doesn't get copied to SARM at run time?

Richard Chen75
Intellectual 550 points
Part Number: TM4C123GH6PM

Tool/software: Code Composer Studio

Hi all, I am looking for some example boot loader code that doesn't get copied to SRAM, does it exist? My understanding is that the benefit of copying the boot loader from flash to SRAM is that it can upgrade the boot loader itself. In my case, I don't need this feature, as I don't need to update the boot loader in the field.

Thanks

Richard

  • 0
    TI__Guru**** 191156 points
    Hi Richard,
    This is not possible. You cannot execute code from the flash while programming the flash. This is the reason the program must first be copied to the SRAM. Please see below excerpt from the datasheet.

    During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory
    is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation
    is complete. If instruction execution is required during a Flash memory operation, the code that is
    executing must be placed in SRAM and executed from there while the flash operation is in progress.
  • 0 in reply to Charles Tsai
    Guru 117855 points

    Hi Charles,

    Well explained - perhaps of use/value ... very recently this forum noted that a "4C129" MCU (I cannot recall the exact device) provided "Two Flash Banks" - and if memory serves (adult beverage consumption last night - has yet to (fully) wear off) such may, "Meet this poster's "SRAM-Free" objective."        (maybe - "fine detail left to you/those ... w/such "inside info.")

  • 0 in reply to cb1_mobile
    TI__Guru**** 191156 points
    Hi cb1,
    In theory, with multi-bank organization it is possible to program one bank while executing another bank as long as the charge pump can support reading and programming multiple banks at the same time. In other TI MCUs this was actually a supported feature but not for TM4C123. However, if you treat the EEprom (flash emulated as EEprom) as another bank, it is a supported feature where you can program the EEprom while running code from the normal bank.
  • 0 in reply to Charles Tsai
    Intellectual 550 points

    Thank you Charles and Cb1 for the reply, sorry for the late response. For the flash in TM4C123G, is there a way to tell if it has multiple banks? I am asking because I am able to write to the top 1K flash from my application that resides and runs within the first/Low 64KB flash.

    Thanks

    Richard

  • 0 in reply to Richard Chen75
    TI__Guru**** 191156 points

    Hi Richard,

     I guess I need to revise my earlier statement that it is not possible to write and read the same bank at the same time. Here is the datasheet excerpt again:

    During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory

    is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation

    is complete. If instruction execution is required during a Flash memory operation, the code that is

    executing must be placed in SRAM and executed from there while the flash operation is in progress.


    I think the reason that it works is because the CPU who is trying to access the flash is put in wait state until the current flash operation (program or ease) is complete. Refer to the flash memory program/erase time for details. The erase time can be up to 500ms. During this time the CPU will be held off. You might have a watchdog that can trip reset if the CPU is not responding for this long or other tasks that require the service of the CPU.  Don't you have code residing from the beginning of the flash bank where you are erasing itself?

  • 0 in reply to Charles Tsai
    Intellectual 550 points
    Thanks Charles for the clarification. You brought up a good point that the watch dog might trip reset during the flashing erasing process, something that I need to keep in mind in the future.

    In my usage case, I have the code residing in the first 40KB of the flash, however the flash that I am going to write is the portion after that. I was able to do so BTW, and have developed a flash based boot loader that is able to start an application residing at a different location in the flash, the code runs from flash, and the SRAM is just used for stack and BSS segments etc for the boot loader first, which will later be exclusively owned by the user application once it is launched.

    Thanks!
    Richard