Part Number: RM57L843
Hello,
In the RM when you swap flash and sram (*0xffffffc4 = 5) there is this statement:
"NOTE: After the swap with the flash memory mapped to 0x08000000, only 512kB of the flash memory from 0x08000000 to 0x0807FFFF will be accessible by the bus masters."
I did a few experiments.
1) All remapped flash cells out to the 4MB limit are present and can be written. (0x0800_0000 .. 0x0840_0000).
2) All remapped flash cells can be executed out past the 512k size mentioned above. (I put one million add r0,r0,#1s and the answer was corr).
I guess the CPU is... a special bus master?
What I am doing here is planning to run the SafeTi diags from flash sector0 and then via some nasty code, swap the flash and sram and begin loading an exec from sector1... a mix of ram and flash.
The loaded exec cannot use the vector format hardcoded by the SafeTi diags. (its legacy code that doesn't use vectored interrupts).
tnx
Hedley
