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TM4C1294NCPDT: Clock issue with SPI daisy chain.

Prasanna Nandaragi
Prodigy 40 points
Part Number: TM4C1294NCPDT

Hello All,

We are trying to establish SPI daisy by connecting Common CS, CLK and MOSI to all 4 16 bit(frame) slaves. And connecting last device DO to MISO. So, I presume this setup would require 16 CLOKS x 4 device = 64 clocks to be issued for every SPI frame which would feed data for all the 4 devices. However, the 'bitcount' configuration is not working for more than 16 count. Is this the limitation with the TI RTOS driver implementation or the processor HW implementation? Or we are missing something here. Can anybody suggest please. 

Please note that when the clock count is set to 16, we are seeing the 16 clocks and CS low for this duration. But when we just change the bit count to 32, clocks are not coming out.

Please suggest what could be wrong.

Thanks in advance.

  • 0
    TI__Guru 72500 points
    Hello Prasanna,
    Welcome to the forum.
    Something does not make sense in what you described, but perhaps it is just my understanding of what you are saying. If MOSI is common to all four slave devices, you only need 16 clocks, but all four devices will get the same data. What is commonly done is that SSI TX (MOSI) is attached to DI of the first device, DO of the first device is attached to DI of the second, and so on, until DO of the fourth device is attached to SSI RX (MISO) of the TM4C. Then you would need 64 clocks to load all four devices.

    Now concerning CS. You did not mention what the four slave devices are, but if they require CS to go high to latch the data that was shifted, then you want CS low, then clock out 64 bits and then CS to go high. You can do this by using the pin attached to CS as a GPIO and having software set it low, do 4 16-bit SSI transmissions and then have software set the CS GPIO high.

    The other option is to use Full Duplex Advanced mode and use the SSI FSS signal to control the CS. You must enable SSI FSSHLDFRM (FSS hold frame) so that the FSS signal goes low on at the first transmission and stays low until all data has been emptied from the SSI FIFO. You then do 8 writes of 8-bits each to the SSI. (The 8 bytes, or 64 bits are loaded into the FIFO and the transmission starts.) You need to be sure the FIFO is empty before doing another transmission to ensure that the FSS signal goes high.