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TMS570LC4357: Td(parallel_out)

Christopher TRITANT
Expert 1080 points

Part Number: TMS570LC4357

Hello,

We are currently in development using the TMS570LC4357 component.

By parsing the Datasheet "SPNS195C", we are finding in §5.10.2 "Output Timings" , the "Td(parallel_out)" timing in the Table 5-6 but  in the related figure 5-5 just above, the timing is not described.

Is this timing described in another figure or only the definition given in the Table 5-6 ?

Best regards,

Christopher.

  • 0
    TI__Guru**** 201216 points
    Hello Christopher,

    This delay is only defined in Table 5-6, and not described by any figure.
  • 0 in reply to QJ Wang
    Expert 1080 points
    Hello,

    Thanks for your first answer.
    However we would need more information about this interesting timing.
    Indeed, the figure 5-5 always shows the rise and fall timings (low and high transition between Vol and Voh), but our understanding is that this "Td(parallel_out)" timing is not included in this figure and must not be since the figure is described for one output and this timing seems to be the differential delay between two outputs written at the same time in the register.

    Is this correct or is there another explanation ?

    Best regards,
    Christopher
  • 0 in reply to QJ Wang
    Expert 1080 points
    Hello,

    Thanks for your first answer.
    However we would need more information about this interesting timing.
    Indeed, the figure 5-5 always shows the rise and fall timings (low and high transition between Vol and Voh), but our understanding is that this "Td(parallel_out)" timing is not included in this figure and must not be since the figure is described for one output and this timing seems to be the differential delay between two outputs written at the same time in the register.

    Is this correct or is there another explanation ?

    Best regards,
    Christopher
  • 0 in reply to Christopher TRITANT
    TI__Guru**** 201216 points
    Hello Christopher,

    Yes , you are right. The figure 5-5 is not designed for the timing of delay.