Hello,
We are currently in development using the TMS570LC4357 component.
By parsing the Datasheet "SPNS195C", we are finding in §6.6.4 "Clock Test Mode" , the "Special Mode" term .
Could you provide us the defintion of this term ?
Moreover, could you confirm that this Special mode (if activated) do not have impact on the global behaviour of the device and drive only the output multiplexor for these output pins ?
Best regards,
Christopher.
Hello Christopher,
The TMS570LC43x microcontrollers support a test mode which allows a user to bring out several different clock sources and clock domains on to the ECLK1. It is very useful information for debug purposes. The choices of the clock sources and clock domains are listed in Table 6-18 (SPNS195C).
Each clock source also has a corresponding clock source valid status flag in the Clock Source Valid Status (CSVSTAT) register. The clock source valid status flags can also be brought out on to the N2HET1[12] terminal in this clock test mode. The choices of the flags are listed in Table 6-19.
The clock test mode is controlled by the CLKTEST register in the system module register frame. The clock test mode is enabled by writing 0x5 to the CLK_TEST_EN field. The signal to be brought out on to the ECLK1 terminal is defined by the SEL_ECP_PIN field, and the signal to be brought out on to the N2HET1[12] terminal is defined by the SEL_GIO_PIN field.
The ECLK can be externally monitored as a safety diagnostic. This mode will not impact on other functions.
