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TMS570LS3137: Register DFSR and error pin

Jordan Zhou
Genius 10170 points
Part Number: TMS570LS3137


Hi,

Two questions about LS3137:

1) Core register DFSR, customer faced an error from DFSR. The value can be 0x008 or 0x80D. What causes this issue? Is there any hardware broken inside LS3137?

2) Error pin, can it be controlled as a GIO, instead of controlling from ESM?

Thanks a lot.

Br, Jordan

  • 0
    TI__Guru**** 198766 points
    Hello Jordan,

    1. The DFSR holds status information regarding the source of the last data abort.
    0x08: Precise external abort --> Check R14 to find which instruction causes this abort
    0x80D: Permission + Write access caused the abort --> The memory address may be protected

    The processor takes the data abort if data should be read from or written to a protected or faulty memory location. This could be because of:
    • The memory location is not implemented
    • The memory location is read or write only in privileged mode (when processor is in User mode)
    • The memory location is read or write protected by the MPU
    • If an error is detected in the data by the ECC checking logic
    Data aborts can be precise or imprecise.

    Precise or Synchronous Aborts aborts for which it is ensured that the exception is taken at the instruction that caused it are called precise aborts or synchronous aborts. This means, that the abort handler could use the SPSR_abt and R14_abt (LR_abt) registers to determine the instruction that generated the abort and the state of the processors when the abort

    2. The nERROR pin can not be used as a general purpose IO pin.