Hello,
We are currently in development using the TMS570LC4357 component.
By parsing the Datasheet "SPNS195C", we are finding in §5.10.2 "Output Timings" , the "Td(parallel_out)" timing in the Table 5-6 but in the related figure 5-5 just above, the timing is not described.
Your first answer was as follows :"This delay is only defined in Table 5-6, and not described by any figure."
However we would need more information about this interesting timing.
Indeed, the figure 5-5 always shows the rise and fall timings (low and high transition between Vol and Voh), but our understanding is that this "Td(parallel_out)" timing is not included in this figure and must not be since the figure is described for one output and this timing seems to be the differential delay between two outputs written at the same time in the register.
Is this correct or is there another explanation ?
Best regards,
Christopher
