TM4C123AH6PM: Datasheet clarification section 8.2.8: uDMA/peripheral interface

Hello twelve12pm,

The point is to allow the uDMA interrupts to indicate when data transfers are completed. Disabling the peripheral interrupts will avoid having multiple interrupts from being sent to the NVIC for portions of the transfer finishing.

That said, when configured correctly, the datasheet also states in Section 8.2.10 that "Unmasked peripheral error interrupts continue to be sent to the interrupt controller." So you would get your UART parity/framing error interrupts etc.

The main key is that setting up interrupts, you want to use the DMA specific interrupts, and not the peripherals own interrupts. I think the wording on that comment could have been better said as "the peripheral must use the DMA interrupts rather than it's own" or something along those lines, as it's really more about what you are enabling than what you are disabling in most cases unless the peripheral was being used without DMA beforehand.

twelve12pm said:

* That all interrupts in the system (those of the peripheral and those belonging to other peripherals as well) are disabled? Will interrupts from timers, etc., fail to trigger if uDMA is being used with a UART for example?

That should not occur in general, but there is an errata item which can come up related to that, DMA#01, and that can cause interrupt from a peripheral pair to be missed.