An FBSLIP error is consistently being set on two TMX570LS20216ASPGE parts that I am working with. I have 5+ parts that appear to be functioning normally. I have reviewed and implemented errata FMZPLL#17, however this does not correct the issue. It was confirmed via use of a XDS510 USB debugger that the Clock Source Valid bits in the CsVSTAT regiser would set prior to the setting of the FBSLIP bit, which makes this issue inconsistent with what is explained in errata FMZPLL#17.
Following are the details:
- 20 MHz oscillator
- FMZPLL Settings: NR=8, NF=104, ODPLL=2, R=1, FM Disabled (This produces a 130MHz output)
- FPLL Settings for FlexRay: OSCIN/2 divider, PLL Prescaler = 1, PLL Multiplier = 8
OBSERVED BEHAVIOR:
The VCLK signal was routed to the ECLK pin and measured with an oscilloscope. The observed result was that the output represented the PLL locked frequency upon initially starting the micro controller, but then reverted to the 20 MHz signal as expected by the configured slip fail action. It was noted that the PLL remained locked at the desired frequency for a significantly longer period of time (on the order of seconds) when the part was initially left unpowered for a period of time before powering it on. After initially setting th eFBSLIP error, successive resets of the part would lock the PLL output for only an extremely brief period before detecting the error (on the order of ms).
FlexRay communications continue to function normally after the FBSLIP error is detected, which indicates to me that the FPLL used for FlexRay is remaining locked. It is my assumption at the moment that the issue I am having is strongly related to the FMZPLL and not the external oscillator, since one of the PLL's on the micro seem to be functioning properly. Additionally, the OSCFAIL bit is not being set.
