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EK-TM4C123GXL: Creating I2S out of SSI Modules

Jackson Hayward
Prodigy 105 points

Part Number: EK-TM4C123GXL

I'm trying to read I2S data using two SSI modules on the EK-TM4C123GXL. I've configured them to run in slave mode at 2.8224 MHz to read the bit clock. I want to use the left/right clock from the I2S master to act as a chip select (CS) which runs at 44.1kHz where a falling edge causes one SSI module to read 24 bits of data and a rising edge to trigger the other.

I think one solution would be to run one SSI module to read the L/R clock as data while the other reads the the 24 bits after each LOW/HIGH and HIGH/LOW transition.

However, I would prefer it if I could use the FSS pin or some other GPIO pin trigger and interrupt that will cause the SSI module to read the data. The problem is that simply attaching an interrupt to the FSS pin cannot read transitions as fast as 44.1kHz.

Is there a solution that will allow me to read transitions as fast as 44.1kHz or would I have to use my second option?

  • 0
    TI__Guru**** 191886 points
    Hi,
    Here is one TM4C123 app note that talks about using SPI to emulate I2S. Please see below link.

    www.ti.com/.../spma042b.pdf
  • 0 in reply to Charles Tsai
    Prodigy 105 points

    Charles,

    Thank you for the example! It looks like the SSI modes only support reading when FSS is pulled low and I don't see in the example where they are able to read when it is asserted. Is a physical NOT gate necessary on one of the FSS lines or is there a way in software to change it to read while asserted instead of deasserted?

    Also, is there a SSI continuous slave receive mode that would allow me to read 24bits as two 12bit data as long as FSS is kept LOW? I'm currently using SSI_FRF_MOTO_MODE_2 with 80MHz/12 bit rate with the interrupt triggering on SSI_RXFF.

    I'm using 

    while((HWREG(SSI1_BASE + SSI_O_SR) & SSI_SR_RNE) == 4) 

    to read all of the contents of the RX FIFO buffer.

    If you could provide any clarification it would be greatly appreciated.

    Thank you,

    Jackson

  • 0 in reply to Jackson Hayward
    Guru 117855 points

    Feel your pain - yet there DO EXIST ARM MCUs which include "Native I2S Ports" - and such "purpose designed/implemented" devices - most always - significantly out-perform - attempts to "kludge together" a replica...

    Have we not learned from the "alchemists?"      No matter how long/hard they  "massaged/assaulted"  multiple  "base"  metals - rarely was "gold" created...

    At some point in time the "extra" time/effort invested - leading to (most always) lesser performance - must receive (some) consideration...

  • 0 in reply to Jackson Hayward
    TI__Guru**** 191886 points
    Hi Jackson,
    The Fss is the CS (chip select) signal in the traditional Motorola (now Freescale -> NXP -> Qualcomn -> Broadcom???) SPI frame format which is active low. There is no software way to invert the polarity.

    If you want to keep the CS active to read the entire 24-bit you will need to configure the frame size for 8-bit and read three 8-bit data in a row. You will need to use the SSIAdvModeSet() to put the QSSI module in the Advanced mode and then use the SSIAdvFrameHoldEnable() API to hold the CS during transfers.