• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 270 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS3137: I/O pin state during reset

Scott Asher
Intellectual 500 points
Part Number: TMS570LS3137

Hello,

I have a question regarding the I/O pin states during nPORRST active. The datasheet says that the I/O pins are configured as inputs with the internal pullup/pulldowns in their "Reset Pull State" as defined in datasheet section 4.3.

My question has to do with the VCC and VCCIO voltage levels required for the I/O pin states during nPORRST as defined in section 4.3 to be true The table in section 5.4 has the recommended operating conditions of VCC between 1.14V and 1.32V, and VCCIO between 3V and 3.6V. For the I/O pins to be guaranteed to be set as inputs with their internal pulls active during nPORRST, does VCC and VCCIO need to be within the voltage ranges defined section 5.4 table or can they be outside the ranges?

If they can be outside these ranges, what are these ranges?

For example, during power-up before VCC and VCCIO reach their minimum levels defined in section 5.4, the nPORRST is already activated. Are the I/O pins guaranteed to be in input state with internal pulls activated when nPORRST is low even before VCC and VCCIO reach their section 5.4 minimum levels? If so, it this guaranteed all the way from 0V or what are minimums?

Can you also provide similar info of the state of the I/O pins when nPORRST is low if VCC and VCCIO go above their section 5.4 maximum levels?

Thanks,

Scott

  • 0
    TI__Guru**** 196306 points

    Hello Scott,

    If the nPORRST is asserted, the I/O pin is always set as input with the internal pull active whatever the VCC and VCCIO are. If the VCC reaches to Vmon max threshold (typical 1.7V), it will assert a power-on reset again.