Part Number: TM4C1290NCZAD
Hi,
I noticed that it seems that UART receive interrupt FIFO level setting (RXIFLSEL in UARTIFLS) also controls at which point the RTS->CTS line gets deactivated. I.e. when RXIFLSEL is set to 1/2 then the interrupt is asserted after receiving 8 bytes and at the same time RTS line becomes inactive until the software reads a byte from the RX FIFO. If I change the setting to 1/8 both events happen after receiving 2 bytes.
This means that RTS always gets briefly deactivated (even if there is a lot of space left in the FIFO) for the time period between when RX FIFO interrupt gets asserted and ISR starts executing and reads a byte from the FIFO.
This is a bit of a problem for the device that I am working on as the sensor that I communicate with through UART stops sending data (and doesn't resume until next measurement is ready) if it detects that RTS->CTS is inactive at any time during the the transmission.
Is it possible to configure an UART interface so that interrupt gets generated a few bytes before RTS gets deasserted? E.g. Interrupt would get generated when RX FIFO is 1/2 full but RTS would only be deactivated after RX FIFO is 7/8 FULL?
I will greatly appreciate any help.
