RM48L952: MinSPI: cannot clear Transfer Group Interrupt

Hello Valerio,

Do you use several group for TX/RX data? In multi-buffer mode, INTVECT0 contains the interrupt for the highest priority transfer group. A read from INTVECT0 automatically causes the next-highest priority transfer group's interrupt status to get loaded into INTVECT0 and its corresponding SUSPEND flag to get loaded into SUSPEND0.

Hi Wang,

I've read about priority in INTVECT0 but now i'm using only the group zero.

After the first transfer I read from INTVECT0 always 0x00000002, which means group zero and it is right. But rereading doesn't get zero as expected but again the same value, even by resetting the flag with mibspiIsTransferComplete().

I tried to extract an minimal example about this, it is based upon TI example "spna231 - High Speed Serial Bus Using the MibSPIP Module", unfortunately I'm not able to make interrupt working as in my application but the problem can be seen even in polling that register and calling mibspiIsTransferComplete().

I changed your example in this way:

use MibSPI1 instead of MibSPI5 (consequently changed DMA request line)
use 128 Mib buffers instead of 64
use one SIMO instead of parallel.
On the other side I have the slave which is another RM48 that move ENA signal and I see receive data correctly.

This worries me because I cannot see a clean way to identify the event "transmission complete".

Here is the main code (IAR tools). Thank you

5100.mainTest.cpp

Hi,
I would like to share my last results on this issue.
It seems that the problem is that I use trigger event ALWAYS, trigger source DISABLED and Oneshot transfer disabled. This because I want to be the software to trigger the transfer.
With this configuration, INTVECT0 and TGINTFLG doesn't work as documented, there is no way to reset them after a transfer.
But enabling Oneshot transfer everything starts to work as documented (Maybe even selecting a trigger for the group would resolve but I've not tried)

This is not the way I want it to work, because I need to re-enable the group every time, losing the possibility to have a continuous transfer with DMA.

Could someone from TI explain the real (beyond official documentation) resetting behavior of INTVECT0 and TGINTFLG?

Thanks for helping!
Valerio

Hello Valerio,

Sorry for late response. I tested on my board, and could not produce your issue:

1. Generate interrupt (TG0): Bit 2 of TgIntVec0 is set, and Bit 16 of TgIntFlg register is set:

2. Clear the the bit by reading the TgIntVec0:

Hello,

I tested with your code, and the interrupt is cleared by reading the TG interrupt vector0: INTVECT0

Hi Wang,
thanks for your attention.
Do you have trigger event ALWAYS, trigger source DISABLED and Oneshot transfer disabled?
It surprises me that it is working for you, is it possible to have your complete example so that I can perform a compare with mine to find out my error?

Regards,
Valerio

Hello Valerio,

I tested it using your code. I copied your function TestEntryPoint() to my sys_main(), and called it in my main().

Yes but I suppose/hope that I did something wrong with my initialization, please post the complete example included halcogen project so that I can perform a comparison with mine.

Thanks and regards,
Valerio

Hi Valerio,

Attached is my project for testing your function. This project was used to test MibSPI loopback.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/312/0777.TMS570LC4357_5F00_MibSPI.7z

Hi Wang,
I looked into your Halcogen configuration, I see your transfer group is set with trigger event TICK, trigger source DISABLED and Oneshot transfer enabled. With that configuration even from me works, as a already stated in previous messages (Mar 6, 2018 4:30 PM and Apr 18, 2018 10:25 AM). The problem is when you set trigger event ALWAYS, trigger source DISABLED and Oneshot transfer disabled.

Thanks and regards,
Valerio