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TMS570LS1224: Need Help in NERROR pin Configuration

Bharat@Honeywell
Prodigy 180 points
Part Number: TMS570LS1224

Hello Team,

We have below set of questions on NERROR pin:

1) Can the NERROR pin be configured as Open drain??

2) What is use of General Purpose Register (GPREG1) (bit[13] controls signal nERROR) ?? What is low EMI output buffer mode??

3) NERROR in Datasheet is mentioned as I/O. Can it be configured as input?? If yes what is usecase? 

4) Datasheet says NERROR has 8 ma drive capability. What does it mean??  Is it Limited to 8 mA or it is the minimum guarnteed value? 

  • 0
    TI__Guru**** 197356 points
    Hello Bharat,

    The nError is an output signal, and it doesn't have any internal pull-up or pull-down after reset. During reset, all the I/O signal is input, and nERROR pin is pulled down. The customer needs to add an external pull-up to the nERROR signal if this pin is used to drive the RESET of other device.

    nError is output only signal, and is not configurable. For example input and open drain.

    GPREG1[13] is used to enable/disable the low-emi mode for nError pin. The low-emi mode is enabled by clearing this bit. The low EMI buffer can reduce the noise ONLY if this noise is coupled from the IO pins or from the core through the silicon. If the noise is generated by the IO toggling itself, Low EMI buffer in this device will not reduce the noise level.

    8mA drive strength means that the load can draw 8mA current while pin can still maintain the appropriate voltage for logic level (Vol, Voh). It doesn't mean the maximum amount of current you can take from the pin.