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TMS570LC4357: L2RAM SECDED functionality

TIDR
Genius 9315 points
Part Number: TMS570LC4357

Hi

The TRM says "To enhance device safety, the L2RAMW has a SECDED malfunction detection feature to ensure that the
SECDED logic is functioning correctly. Every time ECC is calculated for a CPU write data or a read data
for a read-modify-write operation, the results of the ECC correction are compared back again to the
original data value to ensure that the SECDED logic is working correctly. If an error in the SECDED logic
is detected, it will be flagged in the RAMERRSTATUS Register (RAM Error Status)."

In this RMW case, the ECC is being compared against what original value? Can you please clarify?

Thanks!

  • 0
    TI__Guru**** 192486 points
    Hello TIDR,

    Reads from both the level 1 and level 2 SRAM are protected by ECC calculated inside the CPU. The SRAM ECC is located at 0x0840_0000. When Writing data to SRAM, the ECC is also written to ECC area automatically.