Hi,
I have a question about the behavior of EMIF SDRAM controller.
I'm connecting EMIF with a 16-bit data bus SDRAM.
In the Technical Reference Manual, I see that :
- For Write operations, the EMIF_nDQM[1:0] pins are driven to select which bytes of the data word will be written to the SDRAM device. They are also used to mask out entire undesired data words during a burst access.
- For Read operations, the EMIF_nDQM[1:0] pins are driven low during the READ commands and are kept low during the NOP commands that correspond to the burst request.
My understanding is that the EMIF controller can do 8-bit write access to the SDRAM with DQMs signals but always realize 16-bit read access (EMIF_nDQM[0] = EMIF_nDQM[1] = '0' for every read acess).
Can you confirm that my understanding is correct ?
Thank in advance.
