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TMS570LC4357: Problems with self tests on L2FMC Diagnostic Modes

Dirk Jung
Prodigy 80 points
Part Number: TMS570LC4357

Hi,

I am trying to get the self tests for flash L2FMC module, using SafeTI Library 2.4.0 and also implementing on my own (Address Tag Register test, mode 5, which is not done in SafeTI Lib for the TMS570LC4357).

For ECC 1bit test executed with SafeTI Lib function SL_SelfTest_Flash:

Here always the following conditions fails:

if (((((sl_epcREG1->EPCERRSTAT & EPC_ERR_CAM_FULL) == EPC_ERR_CAM_FULL) ||
        ((sl_epcREG1->EPCERRSTAT & EPC_ERR_CAM_OVRFLW) == EPC_ERR_CAM_OVRFLW) ||
        (sl_epcREG1->CAMAVAILSTAT != regBkupCamAvail))) &&
        ((((sl_esmREG->SR1[0]) & BIT(ESM_G1ERR_EPC_SERR))) == (BIT(ESM_G1ERR_EPC_SERR)))) {
/* Clear ESM status registers */
sl_esmREG->SR1[0] = BIT(ESM_G1ERR_EPC_SERR);

....

because in ESM status register the expected bit is not set.

The strange thing is:

If I add a read to the ESM status register (sl_esmREG->SR1[0]), just before the following line triggering the ECC 1bit error it works:

flashread = *(volatile uint32 *)flashBadECC1;

Then I also tried to implement the Address Tag Register Test like proposed in the reference manual of the microcontroller:

It seems to work correctly first, checking only the error flag flashWREG->FEDAC_PASTATUS, the expected bit is set after the test.

According to reference manual the error is also routed to ESM and according to data sheet a ESM group 3 error bit 13 should be set including error reaction: Bus Error, ESM -> nERROR.

If I check esm bit after the test, I do not see the corresponding bit set. 

Then I tested the same as above here, reading the esm status register before the test. And at least when stepping though the code, I see the bit in the esm status register set after the test, but no other reaction. 

Nevertheless for this test after a system reset, the esm group 3 status bit for the expected error is set and the system does not start up as this is checked during startup.

So questions regarding this issue:

Do I have to expect the esm bits set (at least in ECC 1bit  from safety lib it is expected)?

Any idea why reading the status registers does not show the expected bit?

Why does it work with the additional read?

Any other idea what could go wrong?

Best regards, 

Dirk

  • 0
    TI__Guru**** 196526 points
    Hello Dirk,

    1. yes, the ESM bit should be set if the CPU event export is enabled
    2. If the cache is enabled and configured as write through, writing/reading data will experience latency.
    3. Please check the cache setup, and MPU setting (write-through, write-back)
  • 0 in reply to QJ Wang
    Prodigy 80 points

    Hi,

    sorry for the long time until response.

    I had to test some more things.

    Cache is disabled and settings for memory is non cachable as in the demo project provided with the SafeTI Library.

    I now have stripped the project down to the essential parts to show the problem and will attach the project.

    The project is more or less based on the demo project that comes with the SafeTI Library for the TMS570LC4357.

    In HL_sys_startup.c only a normal startup is performed, I removed all CPU and Interconnect tests there.

    The relevant part is based in HL_sys_main.c.

    Here only one test is called: It is the ECC 1bit error test normally provided in SL_SelfTest_Flash in the SafeTI Lib.

    For better analyzing: I have created a function directly in HL_sys_main.c (SelfTest_Flash1). It is based on the funciton SL_SelfTest_Falsh of SafetTI Lib, just all not used #if branches removed, to better see the used code for the relevant microcontroller.

    The relevant lines added to the code from SafeTI Lib can be found at line 221-225 of HL_sys_main.c:

    #if 0

       /* Dummy reading access of ESM Register HACK HACK HACK HACK HACK

        * only with this line the following condition gets satisfied */

       uint32 esmTmp = sl_esmREG->SR1[0];

    #endif

    If these lines are disabled via (if 0) the following condition check fails, because the read of the esm status register does not show the expected bit set. Also after returning from the function investigating the register content in the debugger does not show the bit set.

    But: If they are in the code (if 1) everything works fine.

    Can you explain this behavior?

    Best Regards,

    Dirk.

    6242.SafeTITest.zip

  • 0 in reply to Dirk Jung
    TI__Guru**** 196526 points

    Hello Dirk,

    Please enable the trigger bit before selecting the port A for reading:

  • 0 in reply to QJ Wang
    Prodigy 80 points

    Hi,

    ok, that seems to resolve the problem. And that sequence also corresponds to the test sequence given in the reference manual SPNU563.

    But the code in the provided in my example is exactly the code from SafeTILib 2.4.0, so to correct I have to modify the library code again. You should be aware to do the correction in the next library version, too. 

    What I am wondering is that the provided code in SafeTILib can not be run and have worked in any test on the target so far.

    Best regards,

    Dirk.

  • 0 in reply to Dirk Jung
    TI__Guru**** 196526 points
    Hi Dirk,

    Thanks for reminder. I will ask the SW development to review the code and fix the problem.