TMS570LS3137: Query STCSCSCR[3:0] for STC test continuation after reset

Hello Michael,

First, to clarify, the TRM states that this register is reset to its default values on a power on or "system" reset. A system reset is any reset that causes the nRST pin to be driven low and includes resets from the external assertion of nRST, a SW generated reset, an OSC Fail reset, a WD violation reset, or a debug system reset. It does not include a CPU reset since a CPU reset only impacts the CPU and none of the registers within the device peripheral modules including the Self Test Controller.

In regard to your specific question, the STCSCSCR is the signature compare self test control register. As described it needs to be executed with interval 0 and only interval 0. This means that after the execution of the interval 0 test, there should be a CPU reset as the CPU will reset after the execution of each of the test intervals defined for the STC. After the reset, the code should check if the cause of reset was a CPU reset and, if so, the PC will be modified to continue operation from where it left off which will execute the next interval in the test sequence or execution the code to restore backed up CPU content if required and then continue with the application. In the case where the STC execution is initiated for the purposes of the signature compare self-test, only 1 CPU reset should occur since the signature compare self-test is valid only for interval 0. Once complete, the code should check that the self-test completed successfully and generated the appropriate response according to the configuration of the FAULT_INS bit within this same register.

Hopefully this helps. Please let me know if anything is unclear or if you are observing different behavior than described. Also, as a final note, you mentioned that this in the start up assembly code. Is this something that your company ha manually added? I could be mistaken, but I do not believe that Halcogen includes this test by default.