TM4C129XNCZAD: Double Buffer for Graphics

Hi Brian,
There is a note associated with the LCDDMAConfigSet in the User's guide. Please find below. Would you add LCD_DMA_BURST_16 to the call and see if it makes a difference?

Note:
DMA burst size LCD_DMA_BURST_16 should be set when using frame buffers in external,
EPI-connected memory. Using a smaller burst size in this case is likely to result in occasional
FIFO underflows and associated display glitches.

Hi Brian,
There is a LCD example in section 18.3 of the TivaWare Peripheral Driver Library User's guide. However, it is for single buffer. When the single buffer is used, does the result come out worst compared to the dual buffers or no difference or better?

Hi Charles,

If I may (having been IN the display biz) most all "Single Buffered Memory Schemes" will suffer "Memory Bus Contention" when a, "Display Write" occurs during the "Active Scan" (Display Read) of the Single Buffered Memory.      Such contention is (very) recognizable (disturbing) upon the display - and normally deemed,  "Unacceptable!"

A "Double Buffered Memory" provides the "possibility"  (but not the assurance) - to enable "Display Writes" - to a "separated memory area" ... (even) during the Active Scan of the other (presently scanned) memory.     It usually proves insufficient to, "Just supply a larger memory."     This is so as the "Active Scan" must not be impacted by any "Display Writes" - especially   "those occurring during the "Active Scan."

It may prove, "Outside the capability" of the MCU to, "Continually & Correctly" retrieve data (from one portion of memory) while "Display Writes" (to a separate memory area) are (near) simultaneously in progress!

Such can be detected by monitoring the Address Bus - and observing if the "linear address sequencing"  (noted during, "Non-Write Intervals") becomes "broken/distorted" - during memory writes.     Another means to "Detect such "Double Buffer" capability" - would be to confirm that,  "An MCU write to "Memory Bank_2" - launched "just after" a "memory read" - can occur quickly enough - so as,  "Not to delay" the, "Very next Memory Read from Bank_1."    (such will "disturb" the display!)

Hi cb1,
Thank you for the guidance and sharing your knowledge. I know so well that you are in the display business for a long time. :-) I understand that dual buffer is the preferred method as it is also documented in the datasheet. My rationale for asking to test if the single buffer produce any result that is worst, no difference or better is to understand if there is any DMA setup issue in dual buffer mode or the limitation is simply due to the EPI interface bottleneck. If the single buffer mode produces no difference or even better result than the dual-buffer mode then there could be some DMA setup issue. Certainly we expect the single buffer to produce much worst result. I can't comment on the 480x272 display whether it is too big for the TM4C to handle. The TivaWare example uses a smaller display. Another thing for the poster to check is on the SRAM configuration and the type of SRAM. Will a faster SRAM device help?

BTW, I didn't spot anything wrong with the poster's code.

Hi Charles,

I much doubt that a, "Faster SRAM" will help.     The issue is most surely w/in the MCU - not external memory.

I've added two simple tests to my (earlier) posting.      (Likely arrived during your post's composition.)

If you will - look closely at my (added) final sentence - which may supply the "Death Knell" - to this Double Buffer attempt...

The timing demands of a "480x272" TFT - most likely "bump against/encroach" the limits - of a 120MHz MCU.   (even IF double buffering IS accommodated - especially if - double buffering is accommodated!)

Hi cb1,
I just read your prior reply again. Based on your experience will you be able to comment what display resolution a 120MHz MCU can support? I think that buffering using internal SRAM will help but the available SRAM size will limit the display size.