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TMS570LC4357: TMS570LC4357 PBIST.DLR and PBIST.OVER default value at reset

Franck WARTEL
Intellectual 450 points
Part Number: TMS570LC4357

Hello,

For PBIST.DLR and PBIST.OVER  registers TRM states the following default values:

DLR= 0x00000004

OVER= 0x00000001

however we observed that both registers are read as 0x0 after power on or system.reset:

Can you please tell me if it is an error in the TRM, a variability at device level and especially how I should interpret the warning about not modifying PBIST.DLR(3) from the default value 1, as I am not observing this default value when I leave the register untouched.

Thanks in advance for your support,  

Regards,

Franck

  • 0
    TI__Guru**** 197036 points
    Hi Franck,

    The default value of PBIST DLR register is 0x208, and PBIST OVER is 0x1. To read the register, you need to enable the PBIST clock by programming 0x1 to PACT0 of PACT register.
  • 0 in reply to QJ Wang
    Intellectual 450 points
    Hi QJ,

    I went too fast when reading the TRM and posting my question and indeed bit 3 is supposed to be set to 1 in DLR. However I do not find any reference for bit 9 to be set to 1 after reset in the TRM.

    I clearly missed the PACT0 part in the TRM, however can you please confirm that I can safely understand the "accesss to PBIST will not go through" in case PACT0 is not set as "read as zero with no AXI errors nor interconnect timeouts".

    Thanks,

    Franck.
  • 0 in reply to Franck WARTEL
    TI__Guru**** 197036 points
    Hi Frank,

    The 9th bit is reserved. There are some features which are not implemented in current version devices, for example the PBIST time stamp mode etc.

    Yes, As long as PACT0 bit is 0, any access to PBIST will not go through, and PBIST will remain in an almost zero-power mode.
  • 0 in reply to QJ Wang
    Intellectual 450 points
    Hi QJ,

    Sorry to be picky but even if the bit is reserved the TRM shall properly reflect the default value after reset, and your last answer did not really answer my question as it is a quote of the TRM sentence for which I requested clarifications..

    Do you confirm that TRM is incorrect regarding defaut reset value for reserved bit 9 ?

    Do you confirm that in case PACT0 is not set all PBIST register will behave as Read as Zero with no error ?

    Thanks,

    Franck.
  • 0 in reply to Franck WARTEL
    TI__Guru**** 197036 points
    Hi Franck,

    I understand your comments regarding the reserved bit 9. The feature under bit 9 is either not implemented or not user configurable, this bit is read only. The TRM uses 0 for all reserved bits from bit 5 to bit 31 is not accurate.

    Yes, if PACT0 is not set, all PBIST register will behave as Read as Zero with no error
  • 0 in reply to QJ Wang
    Intellectual 450 points

    Hi QJ,

    Thanks for your answers.  

    Franck.