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TMS570LC4357: ECC Protection for Flash Accesses

Christopher TRITANT
Expert 1080 points
Part Number: TMS570LC4357

Hello,

We are using in the TMS570LC4357 the Flash module.

Regarding the following note included in the section 6.10.3 "ECC Protection for Flash Accesses" in the datasheet of the device: "ECC is permanently enabled in the CPU L2 interface."

Could you confirm our undertsanding about the note in §6.10.3 or correct if needed:
->The signaling mechanism has to be activated (enabled) whereas the computing and checking of ECC is always enabled.

Best regards,

Christopher

  • 0
    TI__Guru**** 197086 points
    Hi Christopher,

    The TMS570LC43x protect all accesses to the on-chip L2 flash memory by dedicated SECDED logic. The SECDED logic implementation uses Error Correction Codes (ECC) for correcting single-bit errors and for detecting multiple-bit errors in the values read from the flash arrays. The SECDED logic inside the CPU is permanently enabled.

    The CPU signals an ECC error through its Event bus. When the CPU detects an ECC single-, or double-bit error on a read from the flash memory, it signals this on a dedicated “Event” bus. This event bus signaling is not enabled by default and must be enabled by the application. The ECC error events exported onto the Event bus is first captured by the Error Profiling Controller (EPC) module and in turn generates error signals that are input to the central Error Signaling Module (ESM).