TMS570LC4357: Unexpected Performance Monitoring Unit Data Cache Miss counter ?

Hello Franck,

This is what we got from ARM regarding to the cache miss:

The PMU events are counting a high number of write instructions, a similar, slightly smaller, number of cache line  evictions, but only a very few cache linefills.

I suspect the reason for these numbers is simply that the processor core only needs to generate this small number of linefills.  

When the processor core is writing to a full cacheline then at first the processor core will trigger a single external linefill based on the first write instruction.  The subsequent write instructions will fill up the store buffer and it is quite possible that the write instructions will write to the full cache line space before the linefill access returns from external memory.  This means that this linefill data is no longer required, and can be discarded when it is returned from the memory system.  Meanwhile, the instructions will start writing to the next cacheline location and will again trigger a linefill.  If the external memory access time is sufficiently long, then eventually the Cortex-R5 core will have the maximum number of outstanding linefills possible and it will not be able to issue anymore until one of the outstanding linefills completes.  When this happens the write instructions can continue to fill up the store buffer before issuing a new linefill.  If the write instructions can fill up a full cacheline they can be added into the cacheline location without ever triggering an external linefill, so the cache location is updated without the need for a linefill access.

So, this is what I suspect is happening in this test, the Cortex-R5 does not need to issue a significant number of linefill accesses because the store instructions are filling up the cacheline locations without needing to issue a linefill.