• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 30 subscribers
  • Views 659 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LAUNCHXL2-570LC43: EMIF SDRAM data corruption

Roman Kosiy
Intellectual 320 points
Part Number: LAUNCHXL2-570LC43

Good day, i have a following problem. I'm using EMIF SDRAM to store a data. When i write data to sdram every 1000ms for some time everything is fine. But sometimes data corruption occurs like this :

What can this be?

  • 0
    TI__Guru**** 197036 points

    Hi Roman,

    Do you mean that the written data and the readback data don't match? Please do another test:

    1. disable cache: _cacheDisable_()

    2. write a bunch of 32-bit words to SDRAM: I use the address as the data in my sample code

    void WRITW32BIT_ADR(unsigned int Start_Address, unsigned int No_Of_Words){

       unsigned int *Addr   = (unsigned int *) Start_Address;

       while(No_Of_Words > 0) {

           *Addr++ = Start_Address++;

           No_Of_Words--;

       }

    }

    3. readback those data and check if they match each other

    unsigned int CHECK_EMIF_MEMORY_32BIT_ADR( unsigned int Start_Address, unsigned int No_Of_Words)
    {
      unsigned int ReadPattern;
      unsigned int *Addr = (unsigned int *) Start_Address;

      while(No_Of_Words > 0)
      {
         ReadPattern = *Addr++;
         if (ReadPattern != Start_Address)
         {
           return (Start_Address);
         }   
         No_Of_Words--;
         Start_Address++;
      }
      return (0);
    }

  • 0 in reply to QJ Wang
    Intellectual 320 points
    I mean, that sometimes readback data dont match, but now always. 85 % of times it matches. but sometimes all of the emif memory (that was not filled with my data) filles with strange data (screenshot).

    1. when i made _cacheDisable(); emif stopped to write data at all.

    readback and write from emif works fine everytime. but sometimes some of the registers are overwritten with this strange data. its not always the same.
  • 0 in reply to Roman Kosiy
    TI__Guru**** 197036 points
    Hi Roman,

    If the cache is enabled and SDRAM is configured as writeback (MPU), the data is written to cache (32kB) first. The SDRAM write operation will not update the SDRAM content every time.

    The EMIF configuration parameters for SDRAM (tRCD, tRC, etc) should match with the values defined in SDRAM datasheet.
  • 0 in reply to QJ Wang
    TI__Guru**** 197036 points

    This is SDRAM configuration used for the SDRAM on HDK (IS42S1640).:

    void emif_SDRAM_StartupInit(void)

    {

    /* USER CODE BEGIN (11) */

    /* USER CODE END */

    volatile uint32 buffer;

    /* Procedure B Step 1:  EMIF Clock Frequency is assumed to be configured in the startup */

    /* Procedure B  Step 2:  Program SDTIMR and SDSRETR to satisfy requirements of SDRAM Device */

    emifREG->SDTIMR  = (uint32)((uint32)2U << 27U)|

      (uint32)((uint32)0U << 24U)|

      (uint32)((uint32)0U << 23U)|

      (uint32)((uint32)0U << 20U)|

      (uint32)((uint32)0U << 19U)|

      (uint32)((uint32)0U << 16U)|

      (uint32)((uint32)1U << 12U)|

      (uint32)((uint32)2U << 8U)|

      (uint32)((uint32)0U << 7U)|

      (uint32)((uint32)0U << 4U)|

      (uint32)((uint32)0U << 3U);

    emifREG->SDSRETR = (uint32)2U;

    /* Procedure B  Step 3:  Program the RR Field of SDRCR to provide 200us of initialization time */

    emifREG->SDRCR   = 1605U;

    /* Procedure B  Step 4:  Program SDRCR to Trigger Initialization Sequence */

    /**  -general clearing of register

    *    -for NM for setting 16 bit data bus

    *    -cas latency

    *    -BIT11_9CLOCK to allow the cl field to be written

    *    -selecting the banks

    *    -setting the pagesize

    */

    emifREG->SDCR   = (uint32)((uint32)0U << 31U)|

     (uint32)((uint32)1U << 14U)|

     (uint32)((uint32)2U << 9U)|

     (uint32)((uint32)1U << 8U)|

     (uint32)((uint32)2U << 4U)|

     (uint32)((uint32)elements_256);

    /* Procedure B  Step 5:  Read of SDRAM memory location causes processor to wait until SDRAM Initialization completes */

    buffer           = *PTR;

    /* prevents optimization */

    buffer           = buffer;

    /* Procedure B  Step 6:  Program the RR field to the default Refresh Interval of the SDRAM*/

    emifREG->SDRCR   = 585U;

    /* Place the EMIF in Self Refresh Mode For Clock Change          */

    /* Must only write to the upper byte of the SDCR to avoid        */

    /* a second intiialization sequence                              */

    /* The byte address depends on endian (0x3U in LE, 0x00 in BE32) */

          *((unsigned char *)(&emifREG->SDCR) + 0x0U) = 0x80;

    /* USER CODE BEGIN (12) */

    /* USER CODE END */

    }