Hello Support,
For STC1 test of CPU, due to errata, both the cores shall be executed together.
Hence the total interval of test cases is 125+3 = 128 = 0x80.
At the end of STC1 run completion with both cores being tested, what should be the expected contents of STCCICR register?
I am thinking it should be 0x0080_0080.
I am getting instead a value of 0x007D_0080, which indicates CORE2 is not running the uSCU test cases.
Can you please confirm if this is the intended design or I have device failure?
I see no time-out error and I also see TEST_DONE=1
Thank you.
Regards
Pashan
