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TMS570LS0714: RTI1 RCLKSRC divider issue versus TRM bit specification

FJ Kime
Prodigy 110 points
Part Number: TMS570LS0714
Other Parts Discussed in Thread: TMS570LS1114

Having trouble using the LP LFO as a source for RT1 per table 2.36 of section 2.5.1.18 of the technical resource manual for the LS09x-07x part.

When attempting to select RTI1DIV to either 2 or 3 (/4 or /8) the counter does not appear to run correctly.

I notice online that only the /2 selection is publicized, and it appears to work.  I am confused as to the following:

sys/rclksrc is 0x00000104   (/2 using lf lpo)

In an accumulation period of 1 second I get (approximately) 5000 counts.

This appears to be a /16 ?

If I attempt to change the '1' (RTI1DIV) to 2 or 3 I get rather bizzare behavior of the RTI interrupt (seems to occur 4 times.)

Would someone please help identify any additional dividers of the lf lpo clock to explain the /16?

Also if there are any errata for this register rclksrc please help locate it.

Note:  I do have the bias turned on and the halcodegen has a call to trimLPO()

PS:  There is another contradiction to the TRM in the generated code (which I guess is to support a variant with a RTI2 timer)

void mapClocks(void)

/** - Setup RTICLK1 and RTICLK2 clocks */

systemREG1->RCLKSRC = (uint32)((uint32) 1U << 24U)   << not in the datasheet ...

| (uint32)((uint32) SYS_VCLK << 16U)

| (uint32)((uint32) 1U << 8U)

| (uint32)((uint32) SYS_VCLK << 0U);

 

  • 0
    TI__Guru 59540 points

    Hello FJ,

    Have you been able to measure the actual LF-LPO frequency itself. Since it has a very wide range of operation, it is difficult to know for certain what the actual frequency is without either using the DCC to measure against the PLL or other clock source or to use the Clock Test output to bring the clock out on a pin to measure it. See section 6.6.3 of the datasheet for details.

    When you leave the default clock source (VCLK) and only change the divider, do you get the correct output and count? I notice in the code snippet above, the clock source for the RTI is configured as SYS_VCLK for RTI1CLK. Is this an error or was this simply meant to show the RTI2CLK configuration part of the code? I am curious because if this is the configuration of the register, the 5000 counts seems more interesting because it is off by a factor of exactly 10000 and could possibly come from a decimal point misplacement  (i.e., being a multiple of the expected 50000000 cycles or counts in 1 second).

    Relative to applicable errata, there are none. Generally you will be able to find any applicable errata in the errata documents posted on the product page on TI.com, i.e., follow this link to the product page - TMS570LS1114, and a link to the errata docs will be at the top of the page.The only special consideration that should be considered is the requirement that the RTICLK be <= VCLK/3 when RCLKSRC is anything other than VCLK as noted in the device TRM. this is for clock synchronization purposes.

    Relative to the writes to the upper bits in the RCLKSRC register, you are correct in assuming this is for devices with two instantiations of the RTI module. Since these writes have no effect for devices without the second RTI module, there was no effort to redact this content from the generic code base.