Hi all, I just entered a post on this however it doesn't seem to be successful (the page loading never finishes and I had to cancel it), so I am going to enter it again here, my apology if it gets duplicated.
I am writing the following sequence to SPI bus via SSI1 module:
"
...
SSIDataPut (SSI1_base, 0x40);
SSIDataPut (SSI1_base, 0x0A);
SSIDataPut (SSI1_base, 0xA0);
"
But I am seeing that /CS line becomes HIGH then LOW between each byte, please see the attached picture, is it normal? Why as the transmit FIFO should be able to hold up to 8 bytes? I lowed down the SPI speed to 100KHz, it doesn't help. Is there a way to have SSI1Fss pin to stay LOW until all bytes are transmitted?
Thanks
Richard