TM4C129ENCPDT: Howto simulate EMAC error

Hi Amir,

 Amit does not support this forum anymore. I will try to answer your questions.

Amir-Yungman said:

1. For logic testing purposes, How can I simulate EMAC_INT_TX_STOPPED, EMAC_INT_RX_STOPPED? Other errors?

 The EMAC DMA will stop when detecting an error. Please see below flowchart depicted in the datasheet.

   I think that when INT_TX_STOPPED bit is set, it is due to errors. This means you may see multiple bits set at the same time. The errors can be due to any of the below listed events in the datasheet. You will need to create one of the below listed errors to simulate the error event. If you properly configure the EMAC using the TivaWare and have the TCP/IP stack, I kind of doubt that you will can easily run into any error events. What you can try to do is by overwriting the EMAC configuration such as the data buffer pointer address with an incorrect/invalid address in the descriptor to see if you can create a bus error. In this case, hopefully the DMA will stop when a bus error is detected.

■ Abnormal Interrupts:
– Transmit Process Stopped (TPS, bit 1): Indicates transmission is stopped.,
– Transmit Jabber Timeout (TJT, bit 3): Indicates the Transmit Jabber Timer expired.
– Receive FIFO Overflow (OVF, bit 4): Indicates the receive buffer had an overflow during frame
reception.
– Transmit Underflow (UNF, bit 5): Indicates the transmit buffer had an underflow during frame
transmission.
– Receive Buffer Unavailable (RU, bit): Indicates the CPU owns the next descriptor in the receive
list and the DMA cannot acquire it.
– Receive Process Stopped (RPS, bit 8): Indicates the receive process entered the STOP state.
– Receive Watchdog Timeout (RWT, bit 9): Indicates a frame length greater than 2 KB is received
(10,240 when Jumbo Frame is enabled)
– Early Transmit Interrupt (ETI, bit 10): Indicates a frame to be transmitted is fully transferred
to the TX FIFO.
– Fatal Bus Error (FBI, bit 13): Indicates a bus error occurred.

Amir-Yungman said:

. When error occurs on a given TX descriptor, will the EMAC continue to the next descriptor?

No, Not according to the flowchart. 

Amir-Yungman said:

3. When error occurs on a given TX descriptor, will the EMAC reset that DES0_TX_CTRL_OWN?

I'm not 100% sure. The OWN bit is set by the CPU and cleared by the EMAC DMA in a normal operation. If the DMA detects an error, the Ethernet operation is suspended and error is generated to the CPU. The CPU will need to diagnose the error source and it is CPU who can re-setup the descriptors and set the OWN bit for DMA again.