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TM4C129ENCPDT: EMAC Interrupt errors handling

Amir-Yungman
Intellectual 410 points
Part Number: TM4C129ENCPDT

Assuming the code enables ROM_EMACIntEnable with only relevant:
EMAC_INT_PHY | EMAC_INT_RECEIVE | EMAC_INT_TRANSMIT | EMAC_INT_TX_UNDERFLOW
And assume any non-listed other error occurs (EMAC_INT_BUS_ERROR, EMAC_INT_RX_NO_BUFFER ... )

1. Will the EMAC stops? will not interrupt the code anymore?
2. Which one might occurs?

and if so
3. How can we detect errors that are NOT listed in the EMACIntEnable?
4. What is recommended to do in that case? Clear any pending interrupts? How?

soft-reset
5. does it clear all pending descriptiors?
6. what is the best way to do it?


  • 0
    TI__Guru**** 190456 points

    Hi,
    i think some of the questions I have answered in the other thread you posted. Enabling the interrupt and detecting/logging an error are two different things. Even if you have not enabled the associated error interrupts, their flags will still set if errors are detected. However, why wouldn't you enable them to notify the CPU in the first place? Without the error interrupts enabled, the DMA may stop/suspend to continue if errors are detected.

    The descriptors are stored in the local RAM. A software reset does not reset the RAM. You will need to reconfigure the descriptors in the event of errors.

  • 0 in reply to Charles Tsai
    Intellectual 410 points
    Hi Charles,
    Thanks for the TWO replies. We still digest them to see how to progress.
    We've notice that most of the ETH drivers source are implemented as described above - "enable only the 3 int source I wrote above"
    I believe all of those ETH programmers know what you are saying about DMA stop, still this is the code and as I don't understand it - I asked....

    We encounter situations where the ETH stops sending any bytes outside to the bus and we havn't found how to debug it.
    The TCP/IP stack above (not lwip) does not know that the driver is not sending anything and all system continue without any data out.

    Can you guide to examples or hints on how to tackle such an issue? as we do not experts in ETH drivers.
    Where to start debugging? PHY? MAC?

    Also, if I will reset the ETH MAC/PHY how will the TCP/IP stack synchronized on that? has stack descriptors pointer become invalid!
    I should reset also the stack?
  • 0 in reply to Amir-Yungman
    TI__Guru**** 190456 points
    Hi Amir,

    Earlier you were asking to "simulate" errors in the Ethernet system. Now it seems that you have a real situation. If this is the case we need to debug the problem differently. Can you answer the below questions?

    1. Can you elaborate the problem? Do you see any error flags? If you do, what are they?
    2. Can you reproduce the problem on a different board with the same project?
    3. Can you run the TivaWare or TI-RTOS ethernet examples? Do you see any problems?
    4. When you ping the host, what happens?
    5. What type of Ethernet application are you running?
    6. On your board design, did you reference the TM4C129 system design guideline concerning the Ethernet interface?