1. TMS570LC43x TRM lists the following feature: "Symmetric dual port (Port A and Port B) for higher performance and concurrent access to different banks from one or more bus masters." How is the port delegation of different operations done? Does the programmer have any control over this?
2. Section 7 of the TRM lists several diagnostic tests that can be performed:
I) 7.6 Deliberate ECC Errors for FMC ECC Checking - Read from single and double-error OTP and verify SEC and expected ESM faults.
II) 7.8.2.2 ECC Data Correction Diagnostic Mode 7: Manipulate the data and/or ECC to verify SEC and expected ESM faults.
III) 7.8.4 SECDED Software Diagnostic: Implicit read L2FMC SECDED test.
Test (III) contains a procedure to verify L2FMC SECDED, but it seems L2FMC SECDED can be better verified by running test (II) or test (I) because we can provide error input. Is my understanding correct here? Do we gain any additional coverage by running test (III), if we have already performed test (I) or (II)?
3. My customer has been experimenting with DIAGMODE=5 (described in 7.8.2.1 Address Tag Register Test Mode 5). They get the expected results for DIAG_BUF_SEL = {4, 5, 6, 7} (ADD_TAG_ERR gets asserted), but not for DIAG_BUF_SEL = {0, 1} (ADD_TAG_ERR remains deasserted) (in other words, they get the expected result when testing Port B buffers but not port A buffers). They also see the same behavior whether executing the test routine out of SRAM or flash (note that step (1) in this test is "Branch to a non-flash region for executing this sequence). Do we have any suggestion or idea what might be happening here?
Thanks!
