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TM4C1294NCPDT: Receive data over RS232 and using FIFO and RX IRQ

Doug Baker
Genius 3420 points
Part Number: TM4C1294NCPDT


I am using a TM4C1294NCPDT with CCS ccs 6.1.2 and TIRTOS 2.16.0.08.

On the TM4C1294NCPDT, I am using UART0 and would like to use the FIFO and the IRQ to receive data from the RS232 device. In my testing, I see I can enable the IRQ and get an interrupt every time I get a character from the RS232 device if the FIFO is off.  If I turn the FIFO on, I see I can set the level of the FIFO to reach before an IRQ is generated.  If I set the FIFO to the lowest level using

#define UART_FIFO_TX1_8         0x00000000  // Transmit interrupt at 1/8 Full

I get an IRQ on every other character so if I receive an odd number or chars I will not get an interrupt to know to go read the last character for the RS232 device.

Currently I have it working by disabling the FIFO but by disabling the FIFO I risk missing a char if for any reason the software gets delayed reading the data before the next char is received.

 

Some code:

   ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);

   ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

   GPIOPinConfigure(GPIO_PA0_U0RX);

   GPIOPinConfigure(GPIO_PA1_U0TX);

   ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);

     ROM_UARTConfigSetExpClk(UART0_BASE, g_ui32SysClock,

                                             ee_prom_rs232GenCfg.baudRate, // 19200, //115200, //9600,

                           (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));

   UARTFIFODisable(UART0_BASE); // this will interrupt every char if FIFO is off.

   UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX1_8, UART_FIFO_RX1_8); // this will interrupt every 2 chars if the FIFO is used.

   Error_init(&eb);

   Hwi_Params_init(&hwiParams);

   myHwi = Hwi_create(INT_UART0_TM4C129, RX232_IrqCallback, &hwiParams, &eb);

UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_TX);

 

What I would prefer is to use the IRQ and the FIFO and be able to get a IRQ on each character received.

 

Am I missing something?

 

Thanks,

Doug

  • 0
    TI__Guru**** 191906 points
    Hi Doug,
    There are 16 entries in the FIFO. If you configure for 1/8 of FIFO to generate the interrupt then you will likely see what you are seeing now whenever there are still two or less data remaining in the FIFO. Can you try with the UART_TXINT_MODE_EOT so that the interrupt is generated when the last data in the FIFO is completely transmitted?
  • 0 in reply to Charles Tsai
    Genius 3420 points
    Doesn't that only apply to the TX from the micro? I don't want to miss a char received from the other device.

    I tried the following but it didn't make any difference.
    UARTTxIntModeSet(UART0_BASE, UART_TXINT_MODE_EOT);

    Doug
  • 0 in reply to Doug Baker
    TI__Guru**** 191906 points
    Hi Doug,
    Disabling the FIFO as you have already tried is one option. Have you tried to generate interrupt based on the receive FIFO reaching the specified threshold instead of the transmit FIFO reaching the watermark level. in the ISR you can try below to make sure all data read from the receive FIFO. There is also a receive timeout interrupt that you can use to make sure that there is no data left in the receive FIFO that is unread before the timer expired.

    while(!UARTCharsAvail(UART0_BASE))
    {
    }
    //
    // Get the character(s) in the receive FIFO.
    //
    while(UARTCharGetNonBlocking(UART0_BASE))
    {
    }
  • 0 in reply to Charles Tsai
    Genius 3420 points

    I do have the IRQ implemented that way where I get a RX IRQ and read till the FIFO is empty. 

    while (UARTCharsAvail(UART0_BASE))

    {

    rxChar = (char) UARTCharGetNonBlocking(UART0_BASE);

    The problem is the micro reads the first char so fast the second char is not in the buffer yet so I don't get the second char.  I'm thinking about using the FIFO so I don't miss anything and just poll or maybe I can use hat I have now where I use IRQ and just turn the FIFO off.

    Doug

  • 0 in reply to Doug Baker
    TI__Guru**** 191906 points
    Hi Doug,
    There is also the receive timeout interrupt (UART_INT_RT) that ensures there is no data left in the receive FIFO that is unread before the timer expired.
  • 0 in reply to Charles Tsai
    TI__Genius 16035 points

    Hi Charles,

    Thank you for your assistance.  In speaking with Doug, he has had success in implementing this albeit without formal qualification and extended testing quite yet.  In summary, the IRQ approach is being chosen over the FIFO implementation (we were both wondering if we have users implementing both in their TM4C Tiva based systems?).  Thereafter, a task can then send data by calling SendNonBlockingRS232() and then the IRQ will handle sending the rest of the characters, as appropriate. That being said, Receive characters come in the IRQ and are buffered until a termination character is found;  then the buffered data are handled as needed.

    Of course, any additional comments or feedback welcomed.  I've forwarded you the code snippet for reference and can also paste it here in this thread for further review once we are comfortable with its content, perhaps to share with others who may be interested to see an example.

    TY,

    Chris